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PDF DS3501 Data sheet ( Hoja de datos )

Número de pieza DS3501
Descripción I2C POT
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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Rev 0; 1/07
High-Voltage, NV, I2C POT with Temp Sensor
and Lookup Table
General Description
The DS3501 is a 7-bit, nonvolatile (NV) digital poten-
tiometer featuring an output voltage range of up to 15.5V.
Programming is accomplished by an I2C-compatible
interface, which can operate at speeds of up to 400kHz.
External voltages are applied at the RL and RH inputs to
define the lowest and highest potentiometer outputs.
The DS3501 contains an on-chip temperature sensor
and associated analog-to-digital converter (ADC). The
ADC output addresses a 36-word NV lookup table
(LUT). The LUT output can drive the pot directly or be
added to an NV initial-value register (IVR) to drive the
pot. This flexible LUT-based architecture allows the
DS3501 to provide a temperature-compensated poten-
tiometer output with arbitrary slope.
Applications
TFT-LCD VCOM Calibration
Linear and Nonlinear Compensation
Instrumentation and Industrial Controls
Mechanical POT Replacement
Optical Transceivers
Pin Configuration and Typical Operating Circuit appear at
end of data sheet.
Features
128 Wiper Tap Points
Full-Scale Resistance: 10kΩ
On-Chip Temperature Sensor and ADC
36-Byte Lookup Table (LUT)
I2C-Compatible Serial Interface
Address Pins Allow Up to Four DS3501s to Share
the Same I2C Bus
Digital Operating Voltage: 2.7V to 5.5V
Analog Operating Voltage: 4.5V to 15.5V
Operating Temperature: -40°C to +100°C
Pin and Software Compatible with ISL95311
(Default Mode)
10-Pin μSOP Package
Ordering Information
PART
TEMP RANGE
DS3501U+
-40°C to +100°C
DS3501U+T&R
-40°C to +100°C
+Denotes a lead-free package.
T&R denotes tape-and-reel.
PIN-PACKAGE
10 µSOP
10 µSOP
Functional Diagram
RH
SDA VOLATILE
SCL WIPER REGISTER
127
126
DS3501
NV IVR
36-BYTE
LUT
NV
MEMORY
125
DECODER
LEVEL
SHIFTER
2
1
CONTROL
CIRCUITRY
A1 AND ADDRESS
A0 DECODE
0
TEMP
SENSOR
AND ADC
RL
RW
______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
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DS3501 pdf
High-Voltage, NV, I2C POT with Temp Sensor
and Lookup Table
(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
220
LUT MODE
170
120 DEFAULT MODE
70
V+ = 15.5V, VCC = 5V
SDA = SCL = VCC; RH, RL, RW ARE FLOATING
20
-40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
Typical Operating Characteristics
SUPPLY CURRENT vs. SUPPLY VOLTAGE
220
LUT MODE
170
120 DEFAULT MODE
70
V+ = 15.5V
SDA = SCL = VCC; RL, RH, RW ARE FLOATING
20
2.7 4.1 5.5
SUPPLY VOLTAGE (V)
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
36
LUT MODE
35
DEFAULT MODE
34
33
32
31
V+ = 15.5V, VCC = 5V
SDA = SCL = VCC; RH, RL, RW ARE FLOATING
30
-40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
INTEGRAL NONLINEARITY
vs. POTENTIOMETER SETTING
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
0
16 32 48 64 80 96 112
POTENTIOMETER SETTING (DEC)
DIFFERENTIAL NONLINEARITY
vs. POTENTIOMETER SETTING
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
0
16 32 48 64 80 96 112
POTENTIOMETER SETTING (DEC)
NAME
SDA
GND
VCC
A1, A0
RH
RW
RL
V+
SCL
Pin Description
PIN DESCRIPTION
1 I2C Serial Data. Input/output for I2C data.
2 Ground Terminal
3 Supply Voltage Terminal
4, 5
Address Select Inputs. Determines I2C slave address. Slave address is 01010A1A0X. (See the Slave
Address Byte and Address Pins section for details).
6 High Terminal of Potentiometer
7 Wiper Terminal of Potentiometer
8 Low Terminal of Potentiometer
9 Wiper Bias Voltage
10 I2C Serial Clock. Input for I2C clock.
_____________________________________________________________________ 5
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DS3501 arduino
High-Voltage, NV, I2C POT with Temp Sensor
and Lookup Table
SDA
tBUF
SCL
STOP
START
tLOW
tHD:STA
tR tF
tHD:DAT
tHIGH
tSU:DAT
NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN).
Figure 3. I2C Timing Diagram
tHD:STA
tSU:STA
REPEATED
START
tSP
tSU:STO
Slave devices: Slave devices send and receive data at
the master’s request.
Bus idle or not busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states.
START condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.
STOP condition: A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a STOP condition.
Repeated START condition: The master can use a
repeated START condition at the end of one data transfer
to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeat-
ed START condition is issued identically to a normal
START condition.
Bit write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into the
device during the rising edge of the SCL.
Bit read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the
data bit is valid at the rising edge of the current SCL
pulse. Remember that the master generates all SCL
clock pulses, including when it is reading bits from the
slave.
Acknowledge (ACK and NACK): An Acknowledge
(ACK) or Not Acknowledge (NACK) is always the 9th bit
transmitted during a byte transfer. The device receiving
data (the master during a read or the slave during a
write operation) performs an ACK by transmitting a 0
during the 9th bit. A device performs a NACK by trans-
mitting a 1 during the 9th bit. Timing for the ACK and
NACK is identical to all other bit writes. An ACK is the
acknowledgment that the device is properly receiving
data. A NACK is used to terminate a read sequence or
indicates that the device is not receiving data.
Byte write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgment from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgment is read using the bit read definition.
Byte read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
____________________________________________________________________ 11
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