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PDF SAA7160 Data sheet ( Hoja de datos )

Número de pieza SAA7160
Descripción PCI Express based audio and video bridge
Fabricantes NXP Semiconductors 
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SAA7160
PCI Express based audio and video bridge
Rev. 01 — 25 February 2008
Product data sheet
1. General description
The SAA7160E and the SAA7160ET are PCI Express based audio and video capture
bridges. Both devices provide ports for capturing video streams, transport streams,
program streams and audio streams with audio functionality like I2S-bus inputs. The
bridges provide audio and video capture function as required for PCI Express applications
like Microsoft ‘multimedia center’.
The target is to cover a range of performance applications like personal video recording
and PC TV cards.
The SAA7160E and the SAA7160ET are highly integrated circuits for TV insertion inside
PC systems. Additional high-speed programming ports enable high integrated system
solutions for multimedia applications.
2. Features
2.1 PCI Express interface SAA7160E and SAA7160ET
I Compliant to PCI Express Base Specification 1.0a
I Native PCI Express
N 64-bit address support
N MSI and INT_A message support
I The PCI Express circuit supports isochronous data traffic intended for uninterrupted
transfer of streaming data like video streaming
N x1 PCI Express endpoint device (2.5 Gbit/s)
N Low jitter and bit error rate
I Type 0 configuration space header
N Single BAR; configurable address range of 17 bits, 18 bits, 19 bits or 20 bits
dependent on application requirements
I DMA write support
N 12 DMA write channels for AV streaming
N Managing up to 8 software buffers per DMA channel
N Buffer size of 2 MB extendable to 4 MB (e.g. HDTV)
N Round-robin arbitration between DMAs
Support overflow recovery if PCI Express bandwidth is not granted in the required
amount
Free Datasheet http://www.datasheet4u.com/

1 page




SAA7160 pdf
NXP Semiconductors
SAA7160
PCI Express based audio and video bridge
5. Pinning information
5.1 SAA7160E package LBGA196
5.1.1 Pinning
ball A1
index area
SAA7160E
2 4 6 8 10 12 14
1 3 5 7 9 11 13
A
B
C
D
E
F
G
H
J
K
L
M
N
P
008aaa085
Transparent top view
Fig 2. Pin configuration for LBGA196
1
A P1_4
B P1_1
C P2_HS
2
P1_5
P1_2
P2_VS
_SOP
3
P1_6
P1_3
P1_0
4
P1_7
P1_HS
P1_VS
_SOP
5
P1_CLK
P5_2
P5_5
6
P5_3
P4_HS
P5_6
7
P4_CLK
P4_7
P5_0
8
P4_4
P4_5
P5_4
9
P5_CLK
P5_7
P5_1
10
P5_HS
P4_6
P5_VS
_SOP
11
P4_1
P4_VS
_SOP
P4_3
12
P4_0
P4_2
P6_0
13
P6_VS
_SOP
P6_VAL
14
P6_HS
P6_CLK
P6_1
P6_2
D P2_CLK
E P2_5
P2_7
P2_4
P2_6
P2_3
F P2_2
P2_1
P2_0
G I2S_SCK_B I2S_SD1_B I2S_WS_B
H P3_VAL
P3_VS
_SOP
I2S_SD0_B
J P3_HS
P3_CLK
P3_7
K P3_6
P3_5
P3_4
L P3_3
P3_2
P3_1
PHI_7
PHI_14
PHI_4
PHI_5
PHI_3
PHI_1
PHI_0
GPIO_0
PHI_8 PHI_RDY_0 PHI_RDN PHI_WRN
PHI_12
VDDDI1
(1V25)
VDDDE1
(3V3)
VDDDE1
(3V3)
VDDDI1
(1V25)
VSS
VSS
VSS
VDDDE3
(3V3)
VSS
VSS
VSS
VDDDE3
(3V3)
VSS
VSS
VSS
PHI_2
VSS
VSS
VSS
VDDD(PCI0)
(1V0)
VDDA(PCI0)
(3V3)
VDDD(PCI1)
(1V0)
VDDA(PCI1)
(3V3)
VDDD(PCI0)
(1V25)
VDDD(PCI1)
(1V25)
VDDDE2
(3V3)
GPIO_29
GPIO_17 GPIO_16 PHI_RDY_1 P6_3
PHI_15
PHI_13
PHI_6
P5_VAL
P6_4
P6_6
P6_5
P6_7
VSS
PHI_10
PHI_11
P4_VAL P2_VAL P1_VAL
VSS
VSS
VSS
VDDDI2
(1V25)
VDDDE2
(3V3)
PHI_9 I2S_SD1_A I2S_WS_A I2S_SD0_A
VDDDI2
(1V25)
PHI_ALE PHI_RDY_3 P1_2_VS I2S_SCK_A
VDDDI(1V25)/ PHI_RDY_2 P1_2_HS P4_5_VS P1_2_FRE
TEST
GPIO_6
TEST1 P4_5_HS GPIO_3 P4_5_FRE
GPIO_26 GPIO_21 GPIO_10 GPIO_13 GPIO_5 GPIO_2
M P3_0
SCL_B
TMS
TRSTN
GPIO_1 PCI_PVT PCI_RESN BOOT_1 SPI_SL_MA GPIO_28 GPIO_18 GPIO_14 GPIO_9
GPIO_4
N SCL_A
P SDA_A
SDA_B
TCK
TDO
TDI
VSS
PCI_PER
_P0
VSS
PCI_PER
_N0
PCI_REF
CLKP
PCI_PET
_P0
PCI_REF
CLKN
PCI_PET
_N0
BOOT_0 SPI_MA_SL GPIO_23 GPIO_20 GPIO_15 GPIO_11
VSS SPI_CLK GPIO_27 GPIO_22 GPIO_19 GPIO_12
GPIO_7
GPIO_8
008aaa087
Fig 3. Pin configuration (LBGA196 top view) for SAA7160E
SAA7160_1
Product data sheet
Rev. 01 — 25 February 2008
© NXP B.V. 2008. All rights reserved.
5 of 57
Free Datasheet http://www.datasheet4u.com/

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SAA7160 arduino
NXP Semiconductors
SAA7160
PCI Express based audio and video bridge
Table 2.
Symbol
P3_4
P3_5
P3_6
P3_7
P3_CLK
P3_HS
Description of functional pins …continued
Pin Type[1] Description
K3 ID
1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes
STV YUV[7:0] bit 4
STV YUV[9:0] bit 6
HDTV UV[9:0] bit 6
2. digital input signal of FGPI_2 or FGPI_3 for parallel
transport stream data of TS3[7:0] bit 4
program stream data of PS3[7:0] bit 4
K2 ID
1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes
STV YUV[7:0] bit 5
STV YUV[9:0] bit 7
HDTV UV[9:0] bit 7
2. digital input signal of FGPI_2 or FGPI_3 for parallel
transport stream data of TS3[7:0] bit 5
program stream data of PS3[7:0] bit 5
K1 ID
1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes
STV YUV[7:0] bit 6
STV YUV[9:0] bit 8
HDTV UV[9:0] bit 8
2. digital input signal of FGPI_2 or FGPI_3 for parallel
transport stream data of TS3[7:0] bit 6
program stream data of PS3[7:0] bit 6
J3 ID
1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes
STV YUV[7:0] bit 7
STV YUV[9:0] bit 9
HDTV UV[9:0] bit 9
2. digital input signal of FGPI_2 or FGPI_3 for parallel
transport stream data of TS3[7:0] bit 7
program stream data of PS3[7:0] bit 7
J2 ID
1. digital input signal of FGPI_2 or FGPI_3 for parallel
transport stream clock of TS3
program stream clock of PS3
2. digital input signal of VIP_1, FGPI_2 or FGPI_3 for
clock signal of parallel video data
J1 ID
digital input signal of VIP_1, FGPI_2 or FGPI_3 for
parallel video data mode STV YUV[9:0] bit 0
parallel video data mode HDTV UV[9:0] bit 0
horizontal synchronization reference in 8-bit STV mode
SAA7160_1
Product data sheet
Rev. 01 — 25 February 2008
© NXP B.V. 2008. All rights reserved.
11 of 57
Free Datasheet http://www.datasheet4u.com/

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