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PDF LC4064B-75T44I Datasheet ( Hoja de datos )

Número de pieza LC4064B-75T44I
Descripción Super Fast High Density PLDs
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo

Total 70 Páginas
		
LC4064B-75T44I Hoja de datos, Descripción, Manual
ispMACHTM 4000V/B/C/Z Family
3.3V/2.5V/1.8V In-System Programmable
January 2004
Coolest Power
SuperFASTTM High Density PLDs
Data Sheet
Features
C
TM
Broad Device Offering
• Multiple temperature range support
High Performance
• fMAX = 400MHz maximum operating frequency
• tPD = 2.5ns propagation delay
• Up to four global clock pins with programmable
– Commercial: 0 to 90°C junction (Tj)
– Industrial: -40 to 105°C junction (Tj)
– Automotive: -40 to 130°C junction (Tj)
clock polarity control
Easy System Integration
• Up to 80 PTs per output
• Superior solution for power sensitive consumer
applications
Ease of Design
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Enhanced macrocells with individual clock,
• Operation with 3.3V (4000V), 2.5V (4000B) or
reset, preset and clock enable controls
1.8V (4000C/Z) supplies
• Up to four global OE controls
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and ret
• Fast path, SpeedLockingTM Path, and wide-PT
interfaces
• Hot-socketing
• Open-drain capability
path • Input pull-up, pull-down or bus-keeper
• Wide input gating (36 input logic blocks) for fast
• Programmable output slew rate
counters, state machines and address decoders
• 3.3V PCI compatible
Zero Power (ispMACH 4000Z) and Low
• IEEE 1149.1 boundary scan testable
Power (ispMACH 4000V/B/C)
• 3.3V/2.5V/1.8V In-System Programmable
• Typical static current 10µA (4032Z)
(ISP™) using IEEE 1532 compliant interface
• Typical static current 1.3mA (4000C)
• I/O pins with fast setup path
• 1.8V core low dynamic power
• Lead-free package options
• ispMACH 4000Z operational down to 1.6V VCC
Table 1. ispMACH 4000V/B/C Family Selection Guide
Macrocells
I/O + Dedicated
Inputs
tPD (ns)
tS (ns)
tCO (ns)
fMAX (MHz)
Supply Voltages (V)
Pins/Package
ispMACH
4032V/B/C
32
30+2/32+4
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
ispMACH
4064V/B/C
64
30+2/32+4/
64+10
2.5
1.8
2.2
400
3.3/2.5/1.8V
44 TQFP
48 TQFP
100 TQFP
ispMACH
4128V/B/C
128
64+10/92+4/
96+4
2.7
1.8
2.7
333
3.3/2.5/1.8V
100 TQFP
128 TQFP
144 TQFP1
1. 3.3V (4000V) only.
2. 128-I/O and 160-I/O congurations.
ispMACH
4256V/B/C
256
64+10/96+14/
128+4/160+4
3.0
2.0
2.7
322
3.3/2.5/1.8V
100 TQFP
144 TQFP1
176 TQFP
256 fpBGA2
ispMACH
4384V/B/C
384
128+4/192+4
ispMACH
4512V/B/C
512
128+4/208+4
3.5
2.0
2.7
322
3.3/2.5/1.8V
3.5
2.0
2.7
322
3.3/2.5/1.8V
176 TQFP
256 fpBGA
176 TQFP
256 fpBGA
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice.
www.latticesemi.com
1
ispm4k_20z

1 page

LC4064B-75T44I pdf
Lattice Semiconductor
Figure 3. AND Array
In[0]
In[34]
In[35]
ispMACH 4000V/B/C/Z Family Data Sheet
PT0
PT1
PT2 Cluster 0
PT3
PT4
Note:
Indicates programmable fuse.
PT75
PT76
PT77
PT78
PT79
Cluster 15
PT80 Shared PT Clock
PT81 Shared PT Initialization
PT82 Shared PTOE
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the ispMACH 4000 family is 4+1 (total 5) product terms.
The software automatically considers the availability and distribution of product term clusters as it ts the functions
within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed
Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for
increased performance.
The enhanced Logic Allocator of the ispMACH 4000 family consists of the following blocks:
• Product Term Allocator
• Cluster Allocator
• Wide Steering Logic
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
to to
n-1 n-2
from from
n-1 n-4
From
n-4
1-80
PTs
Fast 5-PT
Path
5-PT
n To XOR (MC)
Cluster
Individual Product
Term Allocator
to from from
n+1 n+2 n+1
Cluster
Allocator
To n+4
SuperWIDE™
Steering Logic
5

5 Page

LC4064B-75T44I arduino
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
Table 10. ORP Combinations for I/O Blocks with 12 I/Os
I/O Cell
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
Available Macrocells
M0, M1, M2, M3, M4, M5, M6, M7
M1, M2, M3, M4, M5, M6, M7, M8
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M5, M6, M7, M8, M9, M10, M11, M12
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M9, M10, M11, M12, M13, M14, M15, M0
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M13, M14, M15, M0, M1, M2, M3, M4
M14, M15, M0, M1, M2, M3, M4, M5
ORP Bypass and Fast Output Multiplexers
The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the
ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also
allows the register output to bypass the ORP to achieve faster tCO.
Output Enable Routing Multiplexers
The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.
I/O Cell
The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus
maintenance circuitry. Figure 8 details the I/O cell.
Figure 8. I/O Cell
From ORP
GOE 0
GOE 1
GOE 2
GOE 3
VCC
VCCO
From ORP
VCCO
**
*
To Macrocell
To GRP
*Global fuses
Each output supports a variety of output standards dependent on the VCCO supplied to its I/O bank. Outputs can
also be congured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the VCCO supplied to its I/O bank. The I/O standards supported are:
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