DataSheet.es    


PDF IC42S81600L Data sheet ( Hoja de datos )

Número de pieza IC42S81600L
Descripción 4M x 8M x 4 Banks SDRAM
Fabricantes Integrated Circuit Solution 
Logotipo Integrated Circuit Solution Logotipo



Hay una vista previa y un enlace de descarga de IC42S81600L (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! IC42S81600L Hoja de datos, Descripción, Manual

IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
Document Title
4(2)M x 8(16) Bit x 4 Banks (128-MBIT) SDRAM
Revision History
Revision No
History
0A Initial Draft
0B Corrected typo on PIN FUNCTIONS and
revise DC OPERATING CONDITIONS
0C Append two parameters tDPL ,tDAL;correct tRCD
and tRP and modify DC operating condition
0D 1.Obsolete speed grade -7H
2.Support Pb-free package
3.Modify typo in page 16,17
0E Add Industrial range
Change ICC5 from 160mA to 180mA
Draft Date
August 27,2001
May 6,2002
Remark
August 21,2003
September 09,2003
June 11,2004
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
1

1 page




IC42S81600L pdf
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
PIN FUNCTIONS
Symbol
CLK
CKE
Type
Input Pin
Input Pin
CS Input Pin
RAS, CAS, WE
A0-A11
Input Pin
Input Pin
BA0,BA1
DQM, UDQM ,LDQM
Input Pin
Input Pin
DQ0 to DQ15
VDD, VSS
VDDQ, VSSQ
I/O Pin
Power Supply Pin
Power Supply Pin
Function (In Detail)
Master Clock: Other inputs signals are referenecd to the CLK rising edge
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal
clock signals,device input buffers and output drivers. Deactivating the clock
provides PRECHARGE POWER-DOWN and SELF REFRESH operation
(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank).
Chip Select: CS enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS is registered
HIGH. CS provides for external bank selection on systems with multiple
banks. CS is considered part of the command code.
Command Inputs: RAS, CAS and WE (along with CS) define the command
being entered.
Address Inputs: Provide the row address for ACTIVE commands, and the
column address and AUTO PRECHARGE bit for READ/WRITE
commands, to select one location out of the memory array in the respective
bank. The row address is specified by A0-A11. The column address is
specified by A0-A9 (IC42S81600) / A0-A8 (IC42S16800)
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
Din Mask / Output Disable: When DQM is high in burst write, Din for the
current cycle is masked. When DQM is is high in burst read, Dout is
disable at the next but one cycle.
Data Input / Output: Data bus.
Power Supply for the memory array and peripheral circuitry.
Power Supply are supplied to the output buffers only.
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
5

5 Page





IC42S81600L arduino
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
COMMAND TRUTH TABLE
Symbol
DESL
NOP
MRS
ACT
READ
READA
WRIT
WRITA
PRE
PALL
BST
REF
SELF
Command
Device deselect
No operation
Mode register set
Bank activate
Read
Read with auto precharge
Write
Write with auto precharge
Precharge select bank
Precharge all banks
Burst stop
CBR (Auto) refresh
Self refresh
CKE
n-1 n
HX
HX
HX
HX
HX
HX
HX
HX
HX
HX
HX
HH
HL
Notes:
H : High level
X : High or Low level (Don’t care)
L : Low level
V : Valid Data input
A11
CS RAS CAS WE BA A10 A9-A0
HXXXXXX
LHHHXXX
L L L L L LV
L LHHVVV
LHLHVLV
L H L HVHV
LHL L VLV
LHL LVHV
L LHL VLX
L LHL XHX
L HHL XXX
L L LHXXX
L L LHXXX
DQM TRUTH TABLE
Symbol
ENB
MASK
Command
Data Write / Output Enable
Data Mask / Output Disable
CKE
n-1
H
H
n
X
X
DQM
L
H
CKE TRUTH TABLE
Symbol
REF
SELF
Command
Clock suspend mode entry
Clock suspend
Clock suspend mode exit
CBR refresh command
Self refresh entry
Self refresh exit
Power down entry
Power down exit
Current State
Activating
Any
Clock suspend
Idle
Idle
Self refresh
Idle
Power down
CKE
n-1 n
HL
LL
LH
HH
HL
LH
LH
HL
LH
CS RAS CAS WE
XXXX
XXXX
XXXX
LLLH
LLLH
L HHH
HXXX
XXXX
XXXX
Addreess
X
X
X
X
X
X
X
X
X
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
11

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet IC42S81600L.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
IC42S816004M x 8M x 4 Banks SDRAMIntegrated Circuit Solution
Integrated Circuit Solution
IC42S81600L4M x 8M x 4 Banks SDRAMIntegrated Circuit Solution
Integrated Circuit Solution

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar