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PDF 57F68 Data sheet ( Hoja de datos )
| Número de pieza | 57F68 | |
| Descripción | BlueTunes ROM Stereo Headset Solution | |
| Fabricantes | CSR | |
| Logotipo |  |
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 1. QFN - CSR57F68 - CSR  Hay una vista previa y un enlace de descarga de 57F68 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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Features
■ Cost-effective single-chip solution for stereo
headset and wireless speaker applications
■ A2DP1.2 and AVRCP1.0 profiles enabled with
SBC encoder for streaming audio over Bluetooth
and for remote control functionality
■ MP3 decoder for improved audio quality and
reduced power consumption (MP3 decode
functionality requires an appropriate licence from
Thomson, see Section 17.1)
■ Configurable A2DP 5-band EQ
■ High-quality audio 95dB SNR on DAC playback
■ 64MIPS Kalimba DSP coprocessor
■ FastStream, CSR’s low-latency codec for video
and gaming applications
■ HFP 1.5 (includes 3-way calling) and HSP 1.0
support
■ cVc support for echo and noise reduction
■ Low-power consumption: over 10 hours of audio
playback from a 180mAh battery
■ Fully qualified Bluetooth v2.1 + EDR
specification system with support for secure
simple pairing
■ Best-in-class Bluetooth radio with 8dBm transmit
power and -92dBm receive sensitivity
■ 2 integrated linear regulators with 1.5V output
from 1.7V to 1.95V input
■ Integrated switch-mode regulator
■ Integrated lithium battery charger
■ 68-lead 8 x 8 x 0.9mm, 0.4mm pitch QFN package
■ Green (RoHS compliant and no antimony or
halogenated flame retardants)
■ BlueTunes ROM stereo headset solution
development kit available, includes example
design. Order code BTN-003-1A
General Description
Based on _äìÉ`çêÉ∆RJjìäíáãÉÇá~=olj=nck, the
_äìÉqìåÉë=olj=nck integrates a Bluetooth radio,
baseband, DSP, high-quality audio codec, SMPS,
LDO and a battery charger for minimal BOM,
component count and PCB area.
BlueTunes ROM QFN uses advanced DSP features
for the latest stereo enhancements and to improve
audio quality, including SBC and MP3 decoder,
support for FastStream (low-latency codec) and
5‑band EQ.
XTAL
RAM
I2C EEPROM
RF IN
RF OUT
2.4
GHz
Radio
ROM
MCU
UART
I/O Audio In/Out
PIO
Kalimba
DSP
SPI
_äìÉqìåÉë∆=olj=nck
_äìÉqìåÉë=olj=píÉêÉç=eÉ~ÇëÉí=pçäìíáçå
Single-chip Bluetooth® v2.1 + EDR
System
Production Information
BC57F687A05
Issue 3
Applications
■ Stereo headset solution with support for echo and
noise reduction
■ Wireless stereo speakers
BlueTunes ROM QFN includes as standard cVc dual
and single microphone algorithms for echo and noise
suppression.
cVc dual-microphone algorithm can provide >30dB of
noise suppression in both stationary and dynamic
noise conditions such as; babble, road, music and
competing voices. In addition an acoustic echo
canceller is now integrated into the cVc dual-
microphone solution, further enhancing the far-end
user experience.
A cVc single-microphone provides full-duplex echo
cancellation and a 10dB stationary noise suppressor.
BlueTunes ROM QFN includes secure simple pairing,
which greatly simplifies the pairing process, making it
even easier to use a Bluetooth headset.
CS-122312-DSP3
Production Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2008-2009
Page 1 of 74
Free Datasheet http://www.datasheet4u.com/
1 page  
Contents
9.2.2 Multi-slave Operation ............................................................................................................. 31
9.3 I2C Interface ......................................................................................................................................... 31
10 Audio Interface .............................................................................................................................................. 33
10.1 Audio Input and Output ........................................................................................................................ 33
10.2 Audio Codec Interface ......................................................................................................................... 33
10.2.1 Audio Codec Block Diagram .................................................................................................. 34
10.2.2 ADC ........................................................................................................................................ 34
10.2.3 ADC Sample Rate .................................................................................................................. 34
10.2.4 ADC Digital Gain .................................................................................................................... 34
10.2.5 ADC Analogue Gain ............................................................................................................... 35
10.2.6 DAC ........................................................................................................................................ 35
10.2.7 DAC Sample Rate Selection .................................................................................................. 36
10.2.8 DAC Digital Gain .................................................................................................................... 36
10.2.9 DAC Analogue Gain ............................................................................................................... 36
10.2.10 Microphone Input ................................................................................................................... 37
10.2.11 Line Input ............................................................................................................................... 39
10.2.12 Output Stage .......................................................................................................................... 40
10.2.13 Mono Operation ..................................................................................................................... 40
10.2.14 Side Tone ............................................................................................................................... 40
10.2.15 Integrated Digital Filter ........................................................................................................... 41
10.3 AuriStream Codec ............................................................................................................................... 42
11 Power Control and Regulation ...................................................................................................................... 43
11.1 Power Sequencing ............................................................................................................................... 43
11.2 External Voltage Source ...................................................................................................................... 43
11.3 Low-voltage Linear Regulator .............................................................................................................. 44
11.4 Low-voltage Audio Linear Regulator .................................................................................................... 44
11.5 Switch-mode Regulator ....................................................................................................................... 44
11.6 Battery Charger ................................................................................................................................... 45
11.7 Voltage Regulator Enable Pins ............................................................................................................ 45
11.8 Reset, RST# ........................................................................................................................................ 45
11.8.1 Digital Pin States on Reset .................................................................................................... 46
11.8.2 Status after Reset .................................................................................................................. 46
11.9 LED Drivers ......................................................................................................................................... 46
12 Example Application Schematic ................................................................................................................... 48
13 Electrical Characteristics .............................................................................................................................. 49
13.1 Absolute Maximum Ratings ................................................................................................................. 49
13.2 Recommended Operating Conditions .................................................................................................. 49
13.3 Input/Output Terminal Characteristics ................................................................................................. 50
13.3.1 Low-voltage Linear Regulator ................................................................................................ 50
13.3.2 Low-voltage Linear Audio Regulator ...................................................................................... 51
13.3.3 Switch-mode Regulator .......................................................................................................... 52
13.3.4 Battery Charger ...................................................................................................................... 53
13.3.5 Reset ...................................................................................................................................... 54
13.3.6 Regulator Enable ................................................................................................................... 54
13.3.7 Digital Terminals .................................................................................................................... 55
13.3.8 Clocks .................................................................................................................................... 56
13.3.9 LED Driver Pads .................................................................................................................... 56
13.3.10 Mono Codec: Analogue to Digital Converter .......................................................................... 57
13.3.11 Stereo Codec: Digital to Analogue Converter ........................................................................ 58
13.3.12 Auxiliary ADC ......................................................................................................................... 59
13.4 ESD Precautions ................................................................................................................................. 59
14 HCI Power Consumption .............................................................................................................................. 60
15 CSR Green Semiconductor Products and RoHS Compliance ..................................................................... 62
CS-122312-DSP3
Production Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2008-2009
Page 5 of 74
Free Datasheet http://www.datasheet4u.com/
5 Page 
Package Information
3.2 Device Terminal Functions
Bluetooth Radio
Lead Pad Type
RF_N
65 RF
RF_P
64 RF
Supply Domain Description
VDD_RADIO
Transmitter output/switched
receiver
Complement of RF_N
Synthesiser and
Oscillator
XTAL_IN
XTAL_OUT
LO_REF
Lead Pad Type
3
4 Analogue
5
Supply Domain Description
VDD_ANA
For crystal or external clock input
Drive for crystal
Reference voltage to decouple
the synthesiser
SPI Interface
SPI_MOSI
SPI_CS#
SPI_CLK
SPI_MISO
Lead Pad Type
Supply Domain Description
28
Input, with weak internal pull-
down
SPI data input
30
Bidirectional with weak
internal pull-down
29
Bidirectional with weak
internal pull-down
VDD_PADS
Chip select for SPI, active low
SPI clock
31
Bidirectional with weak
internal pull-down
SPI data output
UART Interface
UART_TX
UART_RX
UART_RTS
UART_CTS
Lead Pad Type
9
Output, tristate, with weak
internal pull-down
10
Bidirectional with weak
internal pull-down
Bidirectional CMOS output,
12 tristate, with weak internal
pull-up
11
CMOS input with weak
internal pull-down
Supply Domain Description
UART data output, active high
VDD_UART
UART data input, active high
UART request to send active low
UART clear to send active low
CS-122312-DSP3
Production Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2008-2009
Page 11 of 74
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet 57F68.PDF ] | |
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