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PDF RF65 Data sheet ( Hoja de datos )

Número de pieza RF65
Descripción Low Power Integrated UHF Receiver
Fabricantes HOPERF 
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RF65
Low Power Integrated UHF Receiver With -120dBm High Sensitivity
RFIN
VBAT1&2
VR_ANA
VR_DIG
Power Distribution System
LNA
Single to
Differential
Mixers
Σ/Δ
Modulators
RC
Oscillator
RESET
SPI
NC
NC
NC
Tank
Inductor
Loop
Filter
Division by
2, 4 or 6
Frac-N PLL
Synthesizer
XO
32 MHz
RSSI
AFC
GND
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
GENERAL DESCRIPTION
XTAL
The RF65 is a highly integrated RF receiver capable of
operation over a wide frequency range, including the
3 1 5 , 433,868 and 915 MHz license-free ISM (Industry
Scientific and Medical) frequency bands. Its highly
integrated architecture allows for a minimum of external
components whilst maintaining maximum design flexibility.
All major RF communication parameters are programmable
and most of them can be dynamically set. The RF65 offers
the unique advantage of programmable narrow-band and
wide-band communication modes without the need to
modify external components. The RF65 is optimized for
low power consumption while offering high sensitivity and
channelized operation. TrueRFtechnology enables a
lowcost external component count (elimination of the SAW
filter) whilst still satisfying ETSI and FCC regulations.
APPLICATIONS
Automated Meter Reading
Wireless Sensor Networks
Home and Building Automation
Wireless Alarm and Security Systems
Industrial Monitoring and Control
GND
KEY PRODUCT FEATURES
High Sensitivity: down to -120 dBm at 1.2 kbps
High Selectivity: 16-tap FIR Channel Filter
Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,
80 dB Blocking Immunity, no Image Frequency response
Low current: Rx = 16 mA, 100nA register retention
Constant RF performance over voltage range of chip
FSK Bit rates up to 300 kb/s
Fully integrated synthesizer with a resolution of 61 Hz
FSK, GFSK, MSK, GMSK and OOK demodulation
Built-in Bit Synchronizer performing Clock Recovery
Incoming Sync Word Recognition
115 dB+ Dynamic Range RSSI
Automatic RF Sense with ultra-fast AFC
Packet engine with CRC, AES-128 encryption and 66-
byte FIFO
Built-in temperature sensor and Low Battery indicator
ORDERING INFORMATION
MARKETS
Europe: EN 300-220-1
North America: FCC Part 15.247, 15.249,
15.231
Narrow Korean and Japanese bands
Part Number
Delivery
MOQ / Multiple
RF65
Tape & Reel
3000 pieces
QFN 28 Package - Operating Range [-40;+85°C]
Pb-free, Halogen free, RoHS/WEEE compliant product
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com
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RF65 pdf
ADVANCED COMMUNICATIONS & SENSING
RF65
DATASHEET
Index of Figures
Page
Figure 1. Block Diagram ................................................................................................................................................ 8
Figure 2. Pin Diagram .................................................................................................................................................... 9
Figure 3. Marking Diagram ............................................................................................................................................ 9
Figure 4. TCXO Connection ........................................................................................................................................ 15
Figure 5. Receiver Block Diagram ............................................................................................................................... 17
Figure 6. AGC Thresholds Settings ............................................................................................................................. 19
Figure 7. Cordic Extraction .......................................................................................................................................... 22
Figure 8. OOK Peak Demodulator Description ............................................................................................................ 24
Figure 9. Floor Threshold Optimization ....................................................................................................................... 25
Figure 10. Bit Synchronizer Description ...................................................................................................................... 26
Figure 11. FEI Process ................................................................................................................................................ 27
Figure 12. Optimized Afc (AfcLowBetaOn=1) .............................................................................................................. 28
Figure 13. Temperature Sensor Response ................................................................................................................. 29
Figure 14. Rx Startup - No AGC, no AFC .................................................................................................................... 31
Figure 15. Rx Startup - AGC, no AFC ......................................................................................................................... 31
Figure 16. Rx Startup - AGC and AFC ........................................................................................................................ 31
Figure 17. Listen Mode Sequence (no wanted signal is received) .............................................................................. 33
Figure 18. Listen Mode Sequence (wanted signal is received) ................................................................................... 35
Figure 19. Auto Modes of Packet Handler ................................................................................................................... 36
Figure 20. RF65 Data Processing Conceptual View ................................................................................................... 37
Figure 21. SPI Timing Diagram (single access) .......................................................................................................... 38
Figure 22. FIFO and Shift Register (SR) ..................................................................................................................... 39
Figure 23. FifoLevel IRQ Source Behavior .................................................................................................................. 40
Figure 24. Sync Word Recognition .............................................................................................................................. 41
Figure 25. Continuous Mode Conceptual View ........................................................................................................... 43
Figure 26. Rx Processing in Continuous Mode ........................................................................................................... 43
Figure 27. Packet Mode Conceptual View ................................................................................................................... 44
Figure 28. Fixed Length Packet Format ...................................................................................................................... 45
Figure 29. Variable Length Packet Format .................................................................................................................. 46
Figure 30. Unlimited Length Packet Format ................................................................................................................ 46
Figure 31. CRC Implementation .................................................................................................................................. 50
Figure 32. Manchester Decoding ................................................................................................................................ 50
Figure 33. Data De-Whitening ..................................................................................................................................... 51
Figure 34. POR Timing Diagram ................................................................................................................................. 66
Figure 35. Manual Reset Timing Diagram ................................................................................................................... 67
Figure 36. Application Schematic ................................................................................................................................ 67
Figure 37. Package Outline Drawing ........................................................................................................................... 68
Figure 38. Listen Mode Resolutions, V2a ................................................................................................................... 69
Figure 39. Listen Mode Resolution, V2b ..................................................................................................................... 69
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com
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RF65 arduino
ADVANCED COMMUNICATIONS & SENSING
RF65
DATASHEET
2. Electrical Characteristics
2.1. ESD Notice
The RF65 is a high performance radio frequency device.
Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model) on all pins.
Class B of the JEDEC standard JESD22-A115-A (Machine Model) on all pins.
Class IV of the JEDEC standard JESD22-C101C (Charged Device Model) on pins 2-3-24-26-27, Class III on all other pins.
It should thus be handled with all the necessary ESD precautions to avoid any permanent damage.
2.2. Absolute Maximum Ratings
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 2 Absolute Maximum Ratings
Symbol
VDDmr
Tmr
Tj
Pmr
Supply Voltage
Temperature
Junction temperature
RF Input Level
Description
Min Max Unit
-0.5 3.9 V
-55
+115
°C
-
+125
°C
- +6 dBm
2.3. Operating Range
Table 3 Operating Range
Symbol
VDDop
Top
Clop
ML
Description
Supply voltage
Operational temperature range
Load capacitance on digital ports
RF Input Level
Min Max Unit
1.8 3.6 V
-40 +85 °C
- 25 pF
- 0 dBm
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: [email protected] http://www.hoperf.com
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