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PDF FDMF5820DC Data sheet ( Hoja de datos )
| Número de pieza | FDMF5820DC | |
| Descripción | Smart Power Stage Module | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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September 2013
FDMF5820DC – Smart Power Stage (SPS) Module
with Integrated Temperature Monitor
Features
Ultra-Compact 5 mm x 5 mm PQFN Copper-Clip
Package with Flip Chip Low-Side MOSFET and
Dual Cool Architecture
High Current Handling: 60 A
3-State 3.3 V PWM Input Gate Driver
Dynamic Resistance Mode for Low-Side Drive
(LDRV) Slows Low-Side MOSFET during Negative
Inductor Current Switching
Auto DCM (Low-Side Gate Turn Off) Using
ZCD# Input
Thermal Monitor for Module Temperature Reporting
Programmable Thermal Shutdown (P_THDN)
HS-Short Detect Fault# / Shutdown
Dual Mode Enable / Fault# Pin
Internal Pull-Up and Pull-Down for ZCD# and
EN Inputs, respectively
Fairchild PowerTrench® MOSFETs for Clean
Voltage Waveforms and Reduced Ringing
Fairchild SyncFET™ Technology (Integrated
Schottky Diode) in Low-Side MOSFET
Integrated Bootstrap Schottky Diode
Optimized / Extremely Short Dead-Times
Under-Voltage Lockout (UVLO) on VCC
Optimized for Switching Frequencies up to 1.5 MHz
PWM Minimum Controllable On-Time: 30 ns
Low Shutdown Current: < 3 µA
Optimized FET Pair for Highest Efficiency:
10 ~ 15% Duty Cycle
Operating Ambient Temperature Range:
-40°C to +125°C
Fairchild Green Packaging and RoHS Compliance
Description
The SPS family is Fairchild’s next-generation, fully
optimized, ultra-compact, integrated MOSFET plus
driver power stage solution for high-current, high-
frequency, synchronous buck, DC-DC applications. The
FDMF5820DC integrates a driver IC with a bootstrap
Schottky diode, two power MOSFETs, and a thermal
monitor into a thermally enhanced, ultra-compact, 5 mm
x 5 mm package.
With an integrated approach, the SPS switching power
stage is optimized for driver and MOSFET dynamic
performance, minimized system inductance, and power
MOSFET RDS(ON). The SPS family uses Fairchild's high-
performance PowerTrench® MOSFET technology,
which reduces switch ringing, eliminating the need for a
snubber circuit in most buck converter applications.
A driver IC with reduced dead times and propagation
delays further enhances the performance. A thermal
monitor function warns of a potential over-temperature
situation. A programmable thermal shutdown function
turns off the driver if an over-temperature condition
occurs. The FDMF5820DC incorporates an Auto-DCM
Mode (ZCD#) for improved light-load efficiency. The
FDMF5820DC also provides a 3-state 3.3 V PWM input
for compatibility with a wide range of PWM controllers.
Applications
Servers and Workstations, V-Core and Non-V-Core
DC-DC Converters
Desktop and All-in-One Computers, V-Core and
Non-V-Core DC-DC Converters
High-Performance Gaming Motherboards
High-Current DC-DC Point-of-Load Converters
Networking and Telecom Microprocessor Voltage
Regulators
Small Form-Factor Voltage Regulator Modules
Ordering Information
Part Number Current Rating
Package
FDMF5820DC
60 A
31-Lead, Clip Bond PQFN SPS, 5.0 mm x 5.0 mm Package
Top Mark
FDMF5820DC
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.0.0
www.fairchildsemi.com
1 page  
Electrical Characteristics
Typical value is under VIN=12 V, VCC=PVCC=5 V and TA=TJ=+ 25°C unless otherwise noted. Minimum / Maximum
values are under VIN=12 V, VCC=PVCC=5 V ± 10% and TJ=TA=-40 ~ 125°C unless otherwise noted.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Basic Operation
IQ Quiescent Current
ISHDN
VUVLO
VUVLO_HYST
tD_POR
EN Input
VIH_EN
VIL_EN
RPLD_EN
Shutdown Current
UVLO Threshold
UVLO Hysteresis
POR Delay to Enable IC
High-Level Input Voltage
Low-Level Input Voltage
Pull-Down Resistance
tPD_ENL
EN LOW Propagation Delay
tPD_ENH EN HIGH Propagation Delay
IQ=IVCC + IPVCC, EN=HIGH, PWM=LOW or
HIGH or Float (Non-Switching)
2 mA
ISHDN=IVCC + IPVCC, EN=GND
VCC Rising
3 µA
3.5 3.8 4.1
V
0.4 V
VCC UVLO Rising to Internal PWM Enable
20 µs
2.0
0.8
250
PWM=GND, EN Going LOW to GL Going
LOW
25
PWM=GND, EN Going HIGH to GL
Going HIGH
20
V
V
kΩ
ns
µs
ZCD# Input
VIH_ZCD#
VIL_ZCD#
IPLU_ZCD#
High-Level Input Voltage
Low-Level Input Voltage
Pull-Up Current
tPD_ZLGLL ZCD# LOW Propagation Delay
tPD_ZHGLH ZCD# HIGH Propagation Delay
PWM=GND, ZCD# Going LOW to GL
Going LOW (assume IL <=0)
PWM=GND, ZCD# Going HIGH to GL
Going HIGH
2.0 V
0.8 V
10 µA
10 ns
10 ns
PWM Input
RUP_PWM
RDN_PWM
VIH_PWM
VTRI_Window
VIL_PWM
tD_HOLD-OFF
VHIZ_PWM
Pull-Up Impedance
Pull-Down Impedance
PWM High Level Voltage
3-State Window
PWM Low Level Voltage
3-State Shut-Off Time
3-State Open Voltage
Typical Values: TA=TJ=25°C,
VCC=PVCC=5 V,
Min. / Max. Values:
TA=TJ=-40°C to 125°C,
VCC=PVCC=5 V ±10%
23 kΩ
10 kΩ
2.2 V
1.2 1.8 V
0.8 V
90 130 ns
1.3 1.5 1.7
V
Minimum Controllable On-Time
tMIN_PWM_ON
PWM Minimum Controllable On-
Time
Minimum PWM HIGH Pulse Required for
SW Node to Switch from GND to VIN
30
ns
Forced Minimum GL HIGH Time
tMIN_GL_HIGH Forced Minimum GL HIGH
Minimum GL HIGH Time when LOW
VBOOT-SW detected and PWM
LOW=<100 ns
100 ns
PWM Propagation Delays & Dead Times (VIN=12 V, VCC=PVCC=5 V, fSW=1 MHz, IOUT=20 A, TA=25°C)
tPD_PHGLL
tPD_PLGHL
PWM HIGH Propagation Delay
PWM LOW Propagation Delay
PWM Going HIGH to GL Going LOW,
VIH_PWM to 90% GL
PWM Going LOW to GH(6) Going LOW,
VIL_PWM to 90% GH
15
30
tPD_PHGHH
PWM HIGH Propagation Delay
(ZCD# Held LOW)
PWM Going HIGH to GH Going HIGH,
VIH_PWM to 10% GH (ZCD#=LOW, IL=0,
Assumes DCM)
10
ns
ns
ns
Continued on the following page…
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.0.0
5
www.fairchildsemi.com
5 Page 
Functional Description
The SPS FDMF5820DC is a driver-plus-MOSFET
module optimized for the synchronous buck converter
topology. A PWM input signal is required to properly
drive the high-side and the low-side MOSFETs. The part
is capable of driving speed up to 1.5 MHz.
Power-On Reset (POR)
The PWM input stage should incorporate a POR feature
to ensure both LDRV and HDRV are forced inactive
(LDRV = HDRV = 0) until UVLO > ~ 3.8 V (rising
threshold). After all gate drive blocks are fully powered
on and have finished the startup sequence, the internal
driver IC EN_PWM signal is released HIGH, enabling
the driver outputs. Once the driver POR has finished
(<20 µs maximum), the driver follows the state of the
PWM signal (it is assumed that at startup the controller
is either in a high-impedance state or forcing the PWM
signal to be within the driver 3-state window).
Three conditions below must be supported for normal
startup / power-up.
VCC rises to 5 V, then EN goes HIGH;
EN pin is tied to the VCC pin;
EN is commanded HIGH prior to 5 V VCC reaching
the UVLO rising threshold.
The POR method is to increase the VCC over than UVLO
> rising threshold and EN = HIGH.
Under-Voltage Lockout (UVLO)
UVLO is performed on VCC only, not on PVCC or VIN.
When the EN is set HIGH and VCC is rising over the
UVLO threshold level (3.8 V), the part starts switching
operation after a maximum 20 µs POR delay. The delay
is implemented to ensure the internal circuitry is biased,
stable, and ready to operate. Two VCC pins are
provided: PVCC and VCC. The gate driver circuitry is
powered from the PVCC rail. The user connects PVCC
to VCC through a low-pass R-C filter. This provides a
filtered 5 V bias to the analog circuitry on the IC.
Figure 26. UVLO on VCC
EN / FAULT# (Enable / Fault Flag)
The driver can be disabled by pulling the EN / FAULT#
pin LOW (EN < VIL_EN), which holds both GL and GH
LOW regardless of the PWM input state. The driver can
be enabled by raising the EN / FAULT# pin voltage
HIGH (EN > VIH_EN). The driver IC has less than 3 µA
shutdown current when it is disabled. Once the driver is
re-enabled, it takes a maximum of 20 µs startup time.
EN / FAULT# pin is an open-drain output for fault flag
with an internal 250 kΩ pull-down resistor. Logic HIGH
signal from PWM controller or a ~ 10 kΩ external pull-up
resistor from EN / FAULT# pin to VCC is required to
start driver operation.
Table 1. UVLO and Enable Logic
UVLO EN
Driver State
0X
Disabled (GH & GL = 0)
10
Disabled (GH & GL = 0)
11
Enabled (see Table 2)
1 Open
Disabled (GH & GL = 0)
The EN / FAULT# pin has two functions: enabling /
disabling driver and fault flag. The fault flag signal is
active LOW. When the driver detects a fault condition
during operation, it turns on the open-drain on the EN /
FAULT# pin and the pin voltage is pulled LOW. The
fault conditions are:
High-side MOSFET false turn-on or VIN ~ SW short
during low-side MOSFET turn on;
P-THDN by exceeding 1.5 V on TMON pin.
When the driver detects a fault condition and disables
itself, a POR event on VCC is required to restart the
driver operation.
3-State PWM Input
The FDMF5820DC incorporates a 3-state 3.3 V PWM
input gate drive design. The 3-state gate drive has both
logic HIGH and LOW levels, along with a 3-state
shutdown window. When the PWM input signal enters
and remains within the 3-state window for a defined
hold-off time (tD_HOLD-OFF), both GL and GH are pulled
LOW. This feature enables the gate drive to shut down
both the high-side and the low-side MOSFETs to
support features such as phase shedding, a common
feature on multi-phase voltage regulators.
Table 2. EN / PWM / 3-State / ZCD# Logic States
EN PWM ZCD# GH
GL
0 XX0
0
1 3-State X
0
0
1 0 0 0 1 (IL > 0), 0 (IL < 0)
1 1 01
0
1 0 10
1
1 1 11
0
© 2013 Fairchild Semiconductor Corporation
FDMF5820DC • Rev. 1.0.0
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet FDMF5820DC.PDF ] | |
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