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PDF ILI9335 Data sheet ( Hoja de datos )
| Número de pieza | ILI9335 | |
| Descripción | a-Si TFT LCD Single Chip Driver | |
| Fabricantes | ILI TECHNOLOGY | |
| Logotipo |  |
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ILI9335
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
Datasheet
Version: V0.08
Document No.: ILI9335DS_V0.08.pdf
ILI TECHNOLOGY CORP.
8F, No.38, Taiyuan St., Jhubei City, Hsinchu County 302,
Taiwan, R.O.C
Tel.886-3-5600099; Fax.886-3-5600055
http://www.ilitek.com
Free Datasheet http://www.datasheet4u.com/
1 page  
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
Figures
FIGURE1 SYSTEM INTERFACE AND RGB INTERFACE CONNECTION .................................................................................... 28
FIGURE2 18-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 29
FIGURE3 16-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 30
FIGURE4 9-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 31
FIGURE5 8-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 32
FIGURE 6 DATA FORMAT OF SPI INTERFACE..................................................................................................................... 34
FIGURE7 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) ............................................................... 35
FIGURE8 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI=”1” AND DFM=”10”).................... 36
FIGURE9 DATA TRANSMISSION THROUGH VSYNC INTERFACE)......................................................................................... 37
FIGURE10 MOVING PICTURE DATA TRANSMISSION THROUGH VSYNC INTERFACE ............................................................ 37
FIGURE11 OPERATION THROUGH VSYNC INTERFACE....................................................................................................... 38
FIGURE12 TRANSITION FLOW BETWEEN VSYNC AND INTERNAL CLOCK OPERATION MODES ............................................ 40
FIGURE13 RGB INTERFACE DATA FORMAT ...................................................................................................................... 41
FIGURE14 GRAM ACCESS AREA BY RGB INTERFACE ..................................................................................................... 42
FIGURE15 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE.................................................................. 43
FIGURE16 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MODE ............................................................................ 44
FIGURE17 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE.................................................................................... 45
FIGURE18 INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING ................................................................... 48
FIGURE19 GRAM ACCESS BETWEEN SYSTEM INTERFACE AND RGB INTERFACE .............................................................. 48
FIGURE20 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL ..................................... 50
FIGURE21 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI)...................................................................... 51
FIGURE22 REGISTER SETTING WITH I80 SYSTEM INTERFACE ............................................................................................ 52
FIGURE 23 REGISTER READ/WRITE TIMING OF I80 SYSTEM INTERFACE ........................................................................... 53
FIGURE24 GRAM ACCESS DIRECTION SETTING ............................................................................................................... 58
FIGURE25 16-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................. 59
FIGURE26 8-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................... 60
FIGURE 27 DATA READ FROM GRAM THROUGH READ DATA REGISTER IN 18-/16-/9-/8-BIT INTERFACE MODE.............. 72
FIGURE 28 GRAM DATA READ BACK FLOW CHART ........................................................................................................ 73
FIGURE 29 GRAM ACCESS RANGE CONFIGURATION ........................................................................................................ 76
FIGURE30 GRAM READ/WRITE TIMING OF I80-SYSTEM INTERFACE ............................................................................... 85
FIGURE31 I80-SYSTEM INTERFACE WITH 18-/16-/9-BIT DATA BUS (SS=”0”, BGR=”0”) ................................................. 87
FIGURE32 I80-SYSTEM INTERFACE WITH 8-BIT DATA BUS (SS=”0”, BGR=”0”) .............................................................. 88
FIGURE 33 I80-SYSTEM INTERFACE WITH 18-/9-BIT DATA BUS (SS=”1”, BGR=”1”) ....................................................... 89
FIGURE 34 GRAM ACCESS WINDOW MAP ....................................................................................................................... 90
FIGURE 35 GRAYSCALE VOLTAGE GENERATION............................................................................................................... 91
FIGURE 36 GRAYSCALE VOLTAGE ADJUSTMENT .............................................................................................................. 92
FIGURE 37 GAMMA CURVE ADJUSTMENT ......................................................................................................................... 93
FIGURE 38 EXAMPLE OF RMP(N)0~5 DEFINITION............................................................................................................. 95
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 5 of 112
Version: 0.08
Free Datasheet http://www.datasheet4u.com/
5 Page 
4. Pin Descriptions
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9335
Pin Name
IM3,
IM2,
IM1,
IM0/ID
nCS
RS
nWR/SCL
nRD
nRESET
SDI
SDO
DB[17:0]
I/O Type
Descriptions
Input Interface
Select the MPU system interface mode
IM3 IM2 IM1 IM0
MPU-Interface Mode
DB Pin in use
0 0 0 0 Setting invalid
0 0 0 1 Setting invalid
0 0 1 0 i80-system 16-bit interface
DB[17:10], DB[8:1]
0 0 1 1 i80-system 8-bit interface
DB[17:10]
I IOVcc
0 1 0 ID Serial Peripheral Interface (SPI) SDI, SDO
0 1 1 * Setting invalid
1 0 0 0 Setting invalid
1 0 0 1 Setting invalid
1 0 1 0 i80-system 18-bit interface
DB[17:0]
1 0 1 1 i80-system 9-bit interface
DB[17:9]
1 1 * * Setting invalid
When the serial peripheral interface is selected, IM0 pin is used for the device code ID
setting.
A chip select signal.
I
MPU
IOVcc
Low: the ILI9335 is selected and accessible
High: the ILI9335 is not selected and not accessible
Fix to the GND level when not in use.
A register select signal.
I
MPU
IOVcc
Low: select an index or status register
High: select a control register
Fix to either IOVcc or GND level when not in use.
A write strobe signal and enables an operation to write data when the signal is low.
I
MPU
IOVcc
Fix to either IOVcc or GND level when not in use.
SPI Mode:
Synchronizing clock signal in SPI mode.
I
MPU
IOVcc
A read strobe signal and enables an operation to read out data when the signal is low.
Fix to either IOVcc or GND level when not in use.
I
MPU
IOVcc
A reset pin.
Initializes the ILI9335 with a low input. Be sure to execute a power-on reset after
supplying power.
I
MPU
IOVcc
SPI interface input pin.
The data is latched on the rising edge of the SCL signal.
O
MPU
IOVcc
SPI interface output pin.
The data is outputted on the falling edge of the SCL signal.
Let SDO as floating when not used.
An 18-bit parallel bi-directional data bus for MPU system interface mode
8-bit I/F: DB[17:10] is used.
9-bit I/F: DB[17:9] is used.
16-bit I/F: DB[17:10] and DB[8:1] is used.
I/O
MPU
IOVcc
18-bit I/F: DB[17:0] is used.
18-bit parallel bi-directional data bus for RGB interface operation
6-bit RGB I/F: DB[17:12] are used.
16-bit RGB I/F: DB[17:13] and DB[11:1] are used.
18-bit RGB I/F: DB[17:0] are used.
Unused pins must be fixed to GND level.
ENABLE
I
MPU
IOVcc
Data ENEABLE signal for RGB interface operation.
Low: Select (access enabled)
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 11 of 112
Version: 0.08
Free Datasheet http://www.datasheet4u.com/
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