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PDF TC58NVG2D4BFT00 Data sheet ( Hoja de datos )
| Número de pieza | TC58NVG2D4BFT00 | |
| Descripción | 4 GBIT (512M X 8 BIT) CMOS NAND E2PROM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TC58NVG2D4BFT00 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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TOSHIBA CONFIDENTIAL TC58NVG2D4BFT00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4 GBIT (512M × 8 BIT) CMOS NAND E2PROM (Multi Level Cell)
DESCRIPTION
The TC58NVG2D4B is a single 3.3 V 4 Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 128 pages × 2048 blocks.
The device has two 2112-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block
unit (256 Kbytes + 8 Kbytes: 2112 bytes × 128 pages).
The TC58NVG2D4B is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
Memory cell array
Register
Page size
Block size
TC58NVG2D4B
2112 × 256K × 8
2112 × 8
2112 bytes
(256K + 4K) bytes
• Modes
Read, Read with Data Cache, Reset, Auto Page Program, Auto Page Program with Data Cache, Multi Page
Program with Cache, Auto Block Erase, Status Read, Page Copy
• Mode control
Serial input/output
Command control
• Number of valid blocks
Max 2048 blocks
Min 1968 blocks
• Power supply
VCC = 2.7 V to 3.6 V
• Program/Erase Cycles
TBD Cycles (With 4bit/528Byte ECC)
• Access time
Cell array to register 50 µs max
Serial Read Cycle
50 ns min
• Program/Erase time
Auto Page Program
Auto Block Erase
800 µs/page typ.
3 ms/block typ.
• Operating current
Read (50 ns cycle)
Program (avg.)
Erase (avg.)
Standby
10 mA typ.
10 mA typ.
10 mA typ.
50 µA max
• Package
TC58NVG2D4BFT00 TSOP I 48-P-1220-0.50
(Weight: 0.53 g typ.)
1 2004-07-13C
Free Datasheet http://www.datasheet4u.com/
1 page  
TOSHIBA CONFIDENTIAL TC58NVG2D4BFT00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70 , VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
tCLS
tCLH
tCS
tCH
tWP
tALS
tALH
tDS
tDH
tWC
tWH
tWW
tRR
tRW
tRP
tRC
tREA
tCEA
tCLEA
tALEA
tOH
tRHZ
tCHZ
tREH
tIR
tRHW
tWHC
tWHR
tR
tDCBSYR1
tDCBSYR2
tWB
tRST
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Ready to WE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time
CE Access Time
CLE Access Time
ALE Access Time
Data Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
RE High Hold Time
Output-High-impedance-to- RE Falling Edge
RE High to WE Low
WE High to CE Low
WE High to RE Low
Memory Cell Array to Starting Address
Data Cache Busy in Read Cache (following 31h and 3Fh)
Data Cache Busy in Page Copy (following 3Ah)
WE High to Busy
Device Reset Time (Ready/Read/Program/Erase)
MIN
MAX
UNIT
0⎯
10 ⎯
0⎯
10 ⎯
25 ⎯
0⎯
10 ⎯
20 ⎯
10 ⎯
50 ⎯
15 ⎯
100 ⎯
20 ⎯
20 ⎯
35 ⎯
50 ⎯
⎯ 35
⎯ 45
⎯ 45
⎯ 45
10 ⎯
⎯ 30
⎯ 20
15 ⎯
0⎯
30 ⎯
30 ⎯
30 ⎯
⎯ 50
⎯ 50
⎯ 55
⎯ 200
⎯ 6/6/10/500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
µs
NOTES
5 2004-07-13C
Free Datasheet http://www.datasheet4u.com/
5 Page 
Read Cycle with Data Cache Timing Diagram (1/2)
TOSHIBA CONFIDENTIAL TC58NVG2D4BFT00
CLE
CE
tCLS tCLH
tCS tCH
tWC
WE
tALH tALS
tCLS tCLH
tCS tCH
tCLEA
tCLS tCLH
tCS tCH
tALH tALS tRW tCEA
tCLEA
tCLS tCLH
tCS tCH
tCEA
ALE
RE
I/O
RY / BY
tDS tDH
00h
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0 CA8
to 7 to 11
Column address
N*
PA0 PA8 PA16
to 7 to 15 to 17
Page address
M
tR
tWB
tDS tDH
30h
tDCBSYR1
tRC
tDCBSYR1
tWB
tDS tDH
31h
tRR tREA
DOUT DOUT
N1
tWB
tDS tDH
DOUT
31h
Page address M
Col. Add. 0
tRR tREA
DOUT
0
Page address
M+1
Col. Add. 0
* The column address will be reset to 0 by the 31h command input.
1
Continues to 1 of next page
11 2004-07-13C
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TC58NVG2D4BFT00.PDF ] | |
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