PDF TC58NVG6DDJTA00 Data sheet ( Hoja de datos )

Número de pieza	TC58NVG6DDJTA00
Descripción	64 GBIT (8G X 8 BIT) CMOS NAND E2PROM
Fabricantes	Toshiba
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No Preview Available ! TOSHIBA CONFIDENTIAL TC58NVG6DDJTA00 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 64 GBIT (8G × 8 BIT) CMOS NAND E2PROM (Multi-Level-Cell) DESCRIPTION The TC58NVG6DD is a single 3.3 V 64 Gbit (77,054,607,360 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (16384 + 1280) bytes × 256 pages × 2130 blocks. The device has two 17664-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 17664-byte increments. The Erase operation is implemented in a single block unit (4 Mbytes + 320 Kbytes: 17664 bytes × 256 pages). The TC58NVG6DD is a serial-type memory device which utilizes the DQ pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES • Organization Device capacity Register Page size Block size TC58NVG6DDJTA00 17664 × 256 × 2130 × 8 bits 17664 × 8 bits 17664 bytes (4M + 320 K) bytes • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read • Mode control Serial input/output Command control • Number of valid blocks Min 2018 blocks Max 2130 blocks • Power supply VCC = 2.7 V to 3.6 V • Access time Cell array to register 50 μs typ. (TBD) 100 μs max (TBD) Serial Read Cycle 20 ns min • Program/Erase time Auto Page Program Auto Block Erase 1400 μs/page typ.(TBD) 5 ms/block typ.(TBD) • Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby TBD mA max (per 1 chip) TBD mA max (per 1 chip) TBD mA max (per 1 chip) TBD μA max (per 1 chip) • Package (Weight: TBD g typ.) • FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (17). 1 2011-07-27C Free Datasheet http://www.datasheet4u.com/ 1 page TOSHIBA CONFIDENTIAL TC58NVG6DDJTA00 AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70℃, VCC = 2.7 V to 3.6 V) SYMBOL PARAMETER MIN MAX UNIT tCLS CLE Setup Time 10 ⎯ ns tCLS2 CLE Setup Time 40 ⎯ ns tCLH CLE Hold Time 5 ⎯ ns tCS CE Setup Time 15 ⎯ ns tCS2 CE Setup Time 32 ⎯ ns tCH CE Hold Time 5 ⎯ ns tWP Write Pulse Width 11 ⎯ ns tALS ALE Setup Time 10 ⎯ ns tALH ALE Hold Time 5 ⎯ ns tDS Data Setup Time 5 ⎯ ns tDH Data Hold Time 5 ⎯ ns tWC Write Cycle Time 25 ⎯ ns tWH WE High Hold Time 11 ⎯ ns tADL* Address to Data Loading Time 300 ⎯ ns tWW WP High to WE Low 100 ⎯ ns tRR Ready to RE Falling Edge 20 ⎯ ns tRW Ready to WE Falling Edge 20 ⎯ ns tRP Read Pulse Width 10 ⎯ ns tRC Read Cycle Time 20 ⎯ ns tREA RE Access Time ⎯ 20 ns tCR CE Low to RE Low 10 ⎯ ns tCLR CLE Low to RE Low 10 ⎯ ns tAR ALE Low to RE Low 10 ⎯ ns tRHOH Data Output Hold Time from RE High 25 ⎯ ns tRLOH Data Output Hold Time from RE Low 5 ⎯ ns tRHZ RE High to Output High Impedance ⎯ 60 ns tCHZ CE High to Output High Impedance ⎯ 30 ns tCLHZ CLE High to Output High Impedance ⎯ 30 ns tREH RE High Hold Time 7 ⎯ ns tIR Output-High-impedance-to- RE Falling Edge 0 ⎯ ns tRHW RE High to WE Low 30 ⎯ ns tWHC WE High to CE Low 30 ⎯ ns tWHR1 WE High to RE Low (Status Read) 180 ⎯ ns tWHR2 WE High to RE Low (Column Address Change in Read) 300 ⎯ ns tWB WE High to Busy ⎯ 100 ns tRST Device Reset Time (Ready/Read/Program/Erase) ⎯ 10/10/30/100 μs tCEA CE Access Time ⎯ 25 ns tFEAT Busy time for Set Feature and Get Feature ⎯ 1 μs * tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 5 2011-07-27C Free Datasheet http://www.datasheet4u.com/ 5 Page Read Cycle with Data Cache Timing Diagram (1/2) TOSHIBA CONFIDENTIAL TC58NVG6DDJTA00 CLE CE tCLS tCLH tCH tCS tWC WE tALH tALS tCLS tCLH tCH tCS tCLR tCLS tCLH tCH tCS tALH tALS tRW tCEA tCLR tCLS tCLH tCH tCS tCEA ALE RE DQ[7:0] RY / BY tDS tDH 00h tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH CA0 to 7 CA8 to 14 Column address N* PA0 PA8 PA16 to 7 to 15 to 19 Page address M tR tWB tDS tDH 30h tDCBSYR1 tRC tDCBSYR1 tWB tDS tDH 31h tRR tREA DOUT DOUT 01 tWB tDS tDH DOUT 31h Page address M Col. Add. 0 tRR tREA DOUT 0 Page address M+1 Col. Add. 0 * The column address will be reset to 0 by the 31h command input. 1 Continues to 1 of next page 11 2011-07-27C 11 Page

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