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PDF NCP1901 Data sheet ( Hoja de datos )
| Número de pieza | NCP1901 | |
| Descripción | Primary Side Combination Resonant and PFC Controllers | |
| Fabricantes | ON Semiconductor | |
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NCP1901
Advance Information
Primary Side Combination
Resonant and PFC
Controllers
The NCP1901 is a combination of PFC and half−bridge
resonant controllers optimized for off−line adapter
applications. This device includes all the features needed
to implement a highly efficient and small form factor
adapter. It integrates a critical conduction mode (CrM)
power factor correction (PFC) controller and a half−bridge
controller with a built−in 600 V driver. The half−bridge
stage operates at a fixed frequency. Regulation is achieved
by adjusting the PFC stage output voltage.
This device includes an enable input on the PFC
feedback pin, open feedback loop protection and PFC
overvoltage and undervoltage detectors. Other features
included in the NCP1901 are a 600 V startup circuit and an
adjustable frequency oscillator. The controllers are properly
sequenced, simplifying system design.
Features
• Adjustable Half−Bridge Frequency up to 75 kHz
• Open Feedback Loop Protection
• CrM Power Factor Correction Controller
• PFC Undervoltage Detector
• PFC Overvoltage Detector
• Half−Bridge Controller with 600 V High Side Gate
Drive
• State Machine Ensures Proper Turn−on and Turn−off
of Half−Bridge Stage
• Enable Input on the PFC Feedback Pin Disables
Controllers and Reduces Power
• Controllers are Properly Sequenced for Fault Free
Operation
• Internal 600 V Startup Circuit
• This is a Pb−Free Device
Typical Applications
• High Efficiency Notebook Adapter
• Solid State Lighting
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
http://onsemi.com
SO−20 WB
DW SUFFIX
CASE 751D
SOIC−16
D SUFFIX
CASE 751B
MARKING
DIAGRAM
16
NCP1901G
AWLYWW
1
20
NCP1901
AWLYYWWG
1
NCP1901 = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y or YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NCP1901DR2G
NCP1901DWR2G
SOIC−16
(Pb−Free)
SO−20 WB
(Pb−Free)
2500/Tape & Reel
1000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
February, 2009 − Rev. P0
1
Publication Order Number:
NCP1901/D
Free Datasheet http://www.datasheet4u.com/
1 page  
NCP1901
Table 3. ELECTRICAL CHARACTERISTICS (VHV = open, VPFB = 2.4 V, VPCS = 0 V, VPZCD = 5 V, VPControl = open, VCC = 15 V,
VPDRV = open, VHDRVlo = open, VHVS = 0 V, VHDRVhi = open, VHBoost = 15 V, COSC = 2200 pF, CVREF = 0.1 mF, CPCT = 1000 pF, for typical
values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min Typ Max Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Enable Threshold
Minimum Operating Voltage
Supply Current
Device Disabled/Fault
Device Switching
Startup Current
Startup Circuit Off−State Leakage Current
BANDGAP REFERENCE
VCC Increasing
VCC Decreasing
VCC Decreasing
VPFB = VPUVP(low)
(Note 4)
VCC = VCC (on) – 0.2 V,
VHV = 50 V
VHV = 600 V,
VCC = VCC (on) + 0.2 V
VCC(on)
VCC(enable)
VCC(off)
ICC1
ICC2
Istart
IHV(off)
14.3 15.3 16.3
13.6 14.6 15.6
8.5 9.3 10.0
V
mA
1.0 1.4 2.0
1.5 2.4 3.0
3.0 7.5 10.5 mA
– 15 50 mA
Reference Voltage
OSCILLATOR
CREF = 0.1 mF
VREF
6.605 7.000 7.295
V
Half−Bridge Clock Frequency
Maximum Half−Bridge Clock Frequency
PFC ERROR AMPLIFIER
VHVS = 50 V
COSC = open
fclock
fclock(MAX)
13.5 15.5 16.5 kHz
75 –
– kHz
PFC Feedback Voltage Reference
PFC Feedback Voltage Reference
Regulation with Line
0°C < TJ < 125°C
−40°C < TJ < 125°C
VCC(on) + 0.2 V < VCC < 20 V
VPREF
VPREF(line)
2.42 2.50 2.58
2.40 − 2.60
V
−15 –
15 mV
Error Amplifier Drive Capability
Sink
Source
VPControl = 4 V, VPFB = 5 V
VPControl = 4 V, VPFB = 0.5 V
IEA(SNK)
IEA(SRC)
60 80
−60 −80
–
–
Open Loop Error Amplifier
Transconductance
VPControl = 4 V,
VPFB = 2.4 V and 2.6 V
Gm
60 95
–
Feedback Input Pulldown Current Source
VPFB = 3 V
IPFB 0.5 1.2 1.5
Error Amplifier Maximum Output Voltage
IPControl = 10 mA
VEA(OH)
5.30 5.65 6.00
Error Amplifier Minimum Output Voltage
IPControl = −10 mA
VEA(OL)
2.10 2.25 2.40
Error Amplifier Output Voltage Range
VEA(OH) − VEA(OL)
ΔVEA
3.1 3.4 3.7
3. Resistor/capacitor parallel combination (39 pF || 20 kW) between drive pin and driver supply and between xDRVxx and GND pins.
mA
mS
mA
V
V
V
http://onsemi.com
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
NCP1901
PFC Undervoltage
The NCP1901 safely disables the controller if the PFB
pin is left open. An undervoltage detector disables the
controller if the voltage on the PFB pin is below
VPUVP(low), typically 0.23 V. A 1.2 mA (typical) pull down
current source, IPFB, ensures VPFB falls below VPUVP(low)
if the PFB pin is floating. The PFB pull down current source
affects the PFC output voltage regulation setpoint.
PFC Overvoltage
An overvoltage detector monitors the PFC feedback
voltage and disables the PFC driver if the PFC output voltage
is greater than 5% of its nominal value. PFC drive pulses are
suppressed until the overvoltage condition is removed. The
overvoltage detector tolerance is better than ±2% across the
operating temperature voltage range. The overvoltage
comparator hysteresis is typically 30 mV (1.2%).
PFC Overcurrent
The PFC current is monitored by means of an overcurrent
detector. The PCS pin provides access to the overcurrent
detector. The PFC drive pulse is terminated if the voltage
on the PCS pin exceeds the overcurrent threshold,
VPCS(ILIM). This comparison is done on a cycle by cycle
basis. The overcurrent threshold is typically 0.84 V.
The current sense signal is prone to leading edge spikes
caused by the power switch transitions. The NCP1901 has
leading edge blanking circuitry that blocks out the first
110 ns (typical) of each current pulse.
PFC Driver
The PFC driver source and sink impedances are typically
60 and 15 W, respectively. Depending on the external
MOSFET gate charge requirements, an external driver may
be needed to drive the PFC power switch. A driver as the
one shown in Figure 9 can be easily implemented.
Figure 9. External Driver
Half−Bridge Driver
The half−bridge stage operates at a fixed 50% duty ratio.
The oscillator frequency is divided by two before it is
applied to the half−bridge controller.
The half−bridge controller has a low side driver,
HDRVlo, and a 600 V high side driver, HDRVhi. The built
in high voltage driver eliminates the need for an external
transformer or dedicated driver. A built−in delay between
each drive transition eliminates the risk of cross
conduction. The delay is typically 785 ns. The typical duty
ratio of each half−bridge driver is 48%.
The high side driver is connected between the HBoost
and the HVS pins as shown in Figure 10.
Figure 10. Half−bridge High Side Driver
A boost circuit comprised of Dboost and Cboost generates
the supply voltage for the high side driver. Once HDRVlo
turns on, the HVS pin is effectively grounded through the
external power switch. This allows Cboost to charge to VCC.
Once HDRVlo turns off, HVS floats high and Dboost is
reversed biased. An undervoltage detector monitors the
HBoost voltage. Once the HBoost voltage is greater than
VBoost(UV), typically, 6.1 V, the high side driver is enabled.
The low side driver generally starts before the high side
driver because the boost voltage is generated by the low
side driver switch transitions.
The half−bridge low side driver source and sink
impedances are typically 75 and 15 W, respectively. The
half−bridge high side driver source and sink impedances
are typically 75 and 15 W, respectively. Depending on the
external MOSFETs gate charge requirements, an external
driver may be needed to drive the low and high side power
switches.
Analog and Power Ground
The NCP1901 has an analog ground, GND, and a power
ground, PGND, terminal. GND is used for analog
connections such as VREF and OSC. PGND is used for
high current connections such as the gate drivers. It is
recommended to have independent analog and power
ground planes and connect them at a single point,
preferably at the ground terminal of the system. This will
prevent high current flowing on PGND from injecting
noise in GND. The PGND connection should be as short
and wide as possible to reduce inductance−induced spikes.
http://onsemi.com
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet NCP1901.PDF ] | |
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