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PDF CAT25040 Data sheet ( Hoja de datos )

Número de pieza CAT25040
Descripción (CAT25010 - CAT25040) SPI Serial CMOS EEPROM
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CAT25010, CAT25020,
CAT25040
1-Kb, 2-Kb and 4-Kb SPI
Serial CMOS EEPROM
Description
The CAT25010/20/40 are 1−Kb/2−Kb/4−Kb Serial CMOS
EEPROM devices internally organized as 128x8/256x8/512x8 bits.
They feature a 16−byte page write buffer and support the Serial
Peripheral Interface (SPI) protocol. The device is enabled through a
Chip Select (CS) input. In addition, the required bus signals are a clock
input (SCK), data input (SI) and data output (SO) lines. The HOLD
input may be used to pause any serial communication with the
CAT25010/20/40 device. These devices feature software and
hardware write protection, including partial as well as full array
protection.
Features
20 MHz (5 V) SPI Compatible
1.8 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
16−byte Page Write Buffer
Self−timed Write Cycle
Hardware and Software Protection
Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
PDIP, SOIC, TSSOP 8−Lead and UDFN 8−Pad Packages
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SI
CS
WP
HOLD
SCK
CAT25010
CAT25020
CAT25040
SO
VSS
Figure 1. Functional Symbol
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SOIC−8
V SUFFIX
CASE 751BD
UDFN−8
HU4 SUFFIX
CASE 517AZ
PDIP−8*
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
CS 1
SO
VCC
HOLD
WP SCK
VSS SI
PDIP (L), SOIC (V),
TSSOP (Y), UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
* Not recommended for new designs
Pin Name
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
PIN FUNCTION
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 25
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
1 Publication Order Number:
CAT25010/D

1 page




CAT25040 pdf
CAT25010, CAT25020, CAT25040
Pin Description
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25010/20/40.
CS: The chip select input pin is used to enable/disable the
CAT25010/20/40. When CS is high, the SO output is
tri−stated (high impedance) and the device is in Standby
Mode (unless an internal write operation is in progress).
Every communication session between host and
CAT25010/20/40 must be preceded by a high to low transition
and concluded with a low to high transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low all write operations are inhibited.
HOLD: The HOLD input pin is used to pause transmission
between host and CAT25010/20/40, without having to
retransmit the entire sequence at a later time. To pause,
HOLD must be taken low and to resume it must be taken
back high, with the SCK input low during both transitions.
When not used for pausing, the HOLD input should be tied
to VCC, either directly or through a resistor.
CS
Functional Description
The CAT25010/20/40 devices support the Serial
Peripheral Interface (SPI) bus protocol, modes (0,0) and
(1,1). The device contains an 8−bit instruction register. The
instruction set and associated op−codes are listed in Table 9.
Reading data stored in the CAT25010/20/40 is
accomplished by simply providing the READ command and
an address. Writing to the CAT25010/20/40, in addition to
a WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits in
a Status Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAT25010/20/40 will accept any one of the six instruction
op−codes listed in Table 9 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
Table 9. INSTRUCTION SET (Note 13)
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100 Disable Write Operations
RDSR
0000 0101 Read Status Register
WRSR
0000 0001 Write Status Register
READ
0000 X011 Read Data from Memory
WRITE
0000 X010 Write Data to Memory
13. X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
tCS
tCNH
tCSS
tWH
tWL
tCSH
tCNS
SCK
tH
tSU
SI VALID
IN
HI−Z
SO
tRI
tFI
tV
tHO
VALID
OUT
tV
tDIS
Figure 2. Synchronous Data Timing
HI−Z
Status Register
The Status Register, as shown in Table 10, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 11. The protected
blocks then become read−only.
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CAT25040 arduino
PIN # 1
IDENTIFICATION
D
CAT25010, CAT25020, CAT25040
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL MIN
NOM
MAX
A 5.33
A1 0.38
A2 2.92 3.30 4.95
b 0.36 0.46 0.56
E1 b2 1.14 1.52 1.78
c 0.20 0.25 0.36
D 9.02 9.27 10.16
E 7.62 7.87 8.25
E1 6.10 6.35 7.11
e 2.54 BSC
eB 7.87
10.92
L 2.92 3.30 3.80
TOP VIEW
E
A2
A
A1
b2
L
c
e
SIDE VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
b
eB
END VIEW
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