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PDF IC61S25636D Data sheet ( Hoja de datos )

Número de pieza IC61S25636D
Descripción 8Mb SyncBurst Pipelined SRAM
Fabricantes Integrated Circuit Solution 
Logotipo Integrated Circuit Solution Logotipo



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No Preview Available ! IC61S25636D Hoja de datos, Descripción, Manual

IC61S25632T/D IC61S25636T/D
IC61S51218T/D
Document Title
8Mb SyncBurst Pipelined SRAM
Revision History
Revision No
0A
0B
History
Draft Date
Remark
Initial Draft
1. Move the FT pin for user-configurable Flow
throught or pipelineed operation, That pin can be
NC or connected to VCC for pipelined operation.
Refer to Pin configuration.
2. Revise the power supply charaetoristics at page 12
3. Resive the tKQ of 250 MHZ from 2.5ns to 3ns.
4. Move the 100 MHZ speed grade.
September 24,2001
August 13,2002
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
1
Free Datasheet http://www.datasheet4u.com/

1 page




IC61S25636D pdf
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
SCD
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
256K x 32
Note:Pin 14 connecting to Vcc is acceptable
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BWa -BWd
BWE
GW
CE,CE2,CE2
OE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
DQa-DQd
MODE
SCD
XQ
VCC
GND
VCCQ
ZZ
Synchronous Data Input/Output
Burst Sequence Mode Selection
Single Cycle Deselect/Dual Cycle
Deselect Mode Control
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
5
Free Datasheet http://www.datasheet4u.com/

5 Page





IC61S25636D arduino
IC61S25632T/D IC61S25636T/D
IC61S51218T/D
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Parameter
Value
Unit
TBIAS
Temperature Under Bias
–40 to +85
°C
TSTG
Storage Temperature
–55 to +150
°C
PD Power Dissipation
1.6 W
IOUT Output Current (per I/O)
100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins
–0.5 to VCCQ + 0.5
V
VIN Voltage Relative to GND for
–0.5 to VCC + 0.5
V
for Address and Control Inputs
VCC
Notes:
Voltage on Vcc Supply Relatiive to GND
–0.5 to 4.6
V
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-nent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Circuit Solution Inc.
SSR014-0B 08/13/2002
11
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