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PDF PE83502 Data sheet ( Hoja de datos )

Número de pieza PE83502
Descripción 3.5 GHz Low Power CMOS
Fabricantes Peregrine Semiconductor 
Logotipo Peregrine Semiconductor Logotipo



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Product Description
The PE83502 is a high performance monolithic CMOS
prescaler with a fixed divide ratio of 4. Its operating
frequency range is 1.5 GHz to 3.5 GHz. The PE83502
operates on a nominal 3 V supply and draws only 12 mA.
It is packaged in a small 8-lead MSOP and is ideal for
microwave PLL synthesis solutions.
The PE83502 is manufactured in Peregrine’s patented
Ultra Thin Silicon (UTSi) CMOS process, offering the
performance of GaAs with the economy and integration
of conventional CMOS.
PRODUCT SPECIFICATION
PE83502
Military Operating Temperature Range
3.5 GHz Low Power CMOS
Divide-by-4 Prescaler
Features
High-frequency operation:
1.5 GHz to 3.5 GHz
Fixed divide ratio of 4
Low-power operation: 12 mA
typical @ 3 V across frequency
Small package: 8-lead MSOP
Low Cost
Figure 1. Functional Schematic Diagram
IN
Pre-Amp
DQ
CLK QB
DQ
CLK QB
Output
Buffer
OUT
Figure 2. Package Drawing
3.05
2.85
8-lead MSOP
5.05
4.75
Table 1. Electrical Specifications (ZS = ZL = 50 )
2.85V VDD 3.15 V; -55° C TA 125° C, unless otherwise specified
Parameter
Supply Voltage
Supply Current
Input Frequency (FIN)
Input Power (PIN)
Output Power
Conditions
Minimum
2.85
1500 MHz Fin 3200 MHz
3200 MHz < Fin 3500 MHz
1.5
-5
0
-5
Typical
3.0
13
Maximum
3.15
19
3.5
+10
+10
Units
V
mA
GHz
dBm
dBm
dBm
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
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PE83502 pdf
PE83502
Product Specification
Figure 10. Evaluation Board Schematic Diagram
Figure 11. Evaluation Board Layout
J2-7
10 pF 1000 pF
VDD
IN
J1 CC13
10 nF
10 pF
DEC
GND
GND
OUT
NC
CC12
GND
J3
J4 J5
Evaluation Kit Operation
The MSOP Prescaler Evaluation Board was
designed to help customers evaluate the PE83502
Divide-by-4 Prescaler. On this board, the device
input (pin 2) is connected to connector J1 through a
50 transmission line. A series capacitor (C3)
provides the necessary DC block for the device
input. It is important to note that the value of this
capacitance will impact the performance of the
device. A value of 15pF was found to be optimal for
this board layout; other applications may require a
different value.
The device output (pin 7) is connected to connector
J3 through a 50 transmission line. A series
capacitor (C1) provides the necessary DC block for
the device output. Note that this capacitor must be
chosen to have a low impedance at the desired
output frequency the device. The value of 100pF
was chosen to provide a wide operating range for
the evaluation board.
The board is constructed of a two-layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide above
ground plane model with trace width of 0.030”, trace
gaps of 0.007”, dielectric thickness of 0.028”, metal
thickness of 0.0014” and εr of 4.4. Note that the
predominate mode for these transmission lines is
coplanar waveguide.
J2 provides DC power to the device. Starting from
the lower left pin, the second pin to the right (J2-3)
is connected to the device VDD pin (1). Two
decoupling capacitors (10 pF, 1000 pF) are
included on this trace. It is the responsibility of the
customer to determine proper supply decoupling for
their design application.
The DEC pin (3) must be connected to a low
impedance AC ground for proper device operation.
On the board, two decoupling capacitors (C6 = 10
nF, C4 = 10 pF), located on the back of the board,
perform this function.
Applications Support
If you have a problem with your evaluation kit or if
you have applications questions call (858) 455-0660
and ask for applications support. You may also
contact us by fax or e-mail:
Fax: (858) 455-0770
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
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