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High Bandwidth Multiplying DAC - Analog Devices

Número de pieza AD5425
Descripción High Bandwidth Multiplying DAC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD5425 datasheet

1 Page

AD5425 pdf
AD5425
Parameter
Min Typ Max Unit
Digital THD
50 kHz fOUT
20 kHz fOUT
Output Noise Spectral Density
70 dB
73 dB
25 nV√Hz
SFDR Performance (Wide Band)
50 kHz fOUT
20 kHz fOUT
SFDR Performance (Narrow Band)
67 dB
68 dB
50 kHz fOUT
20 kHz fOUT
Intermodulation Distortion
73 dB
75 dB
79 dB
POWER REQUIREMENTS
Power Supply Range
IDD
Power Supply Sensitivity
2.5
0.4
1 Guaranteed by design and characterization, not subject to production test.
5.5
0.6
5
0.001
V
µA
µA
%/%
Data Sheet
Conditions/Comments
Clock = 1 MHz, VREF = 3.5 V, CCOMP = 1.8 pF
@ 1 kHz
Clock = 2 MHz , VREF = 3.5 V
Clock = 2 MHz, VREF = 3.5 V
f1 = 20 kHz, f2 = 25 kHz, clock = 2 MHz,
VREF = 3.5 V
TA = 25°C, logic inputs = 0 V or VDD
Logic inputs = 0 V or VDD, T = −40°C to +125°C
ΔVDD = ±5%
Rev. C | Page 4 of 24
Free Datasheet http://www.datasheet4u.com/

5 Page

AD5425 arduino
Data Sheet
0.5
TA = 25°C
VDD = 3V
VREF = 0V
0.3
MAX INL
0.1
MAX DNL
–0.1
MIN INL
–0.3
MIN DNL
–0.5
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VBIAS (V)
Figure 10. Linearity vs. VBIAS Voltage Applied to IOUT2
1.4
TA = 25°C
1.2
VDD = 3V
VREF = 0V
1.0
0.8
GAIN ERROR
0.6
0.4
OFFSET ERROR
0.2
0
–0.2
–0.4
0.5
1.0
VBIAS (V)
1.5
Figure 11. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2
0.5
VDD = 5V
VREF = 0V
0.3
MAX INL
0.1
MAX DNL
–0.1
MIN DNL
–0.3
MIN INL
–0.5
0.5
1.0 1.5 2.0
VBIAS (V)
2.5
Figure 12. Linearity vs. VBIAS Voltage Applied to IOUT2
AD5425
2.5
VDD = 5V
VREF = 0V
2.0
1.5
GAIN ERROR
1.0
0.5
OFFSET ERROR
0
–0.5
0.5
1.0 1.5 2.0
VBIAS (V)
2.5
Figure 13. Gain and Offset Errors vs. Voltage Applied to IOUT2
10.0
TA = 25°C
VDD = 5V
8.0 VREF = 2.5V
6.0
4.0
2.0
OFFSET ERROR
0
–2.0
GAIN ERROR
–4.0
0
0.5 1.0 1.5 2.0 2.5
VBIAS (V)
Figure 14. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2
1.0
TA = 25°C
0.8 VDD = 5V
VREF = 2.5V
0.6
0.4
0.2 MAX INL BIAS
MIN INL BIAS
0
–0.2
MAX DNL BIAS
–0.4
MIN DNL BIAS
–0.6
–0.8
–1.0
0
0.5 1.0 1.5
VBIAS (V)
2.0
Figure 15. Linearity vs. VBIAS Voltage Applied to IOUT2
Rev. C | Page 9 of 24
Free Datasheet http://www.datasheet4u.com/

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