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PDF IDT71P73204 Data sheet ( Hoja de datos )

Número de pieza IDT71P73204
Descripción 18Mb Pipelined DDRII SRAM Burst of 4
Fabricantes IDT 
Logotipo IDT Logotipo



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No Preview Available ! IDT71P73204 Hoja de datos, Descripción, Manual

18Mb Pipelined
DDR™II SRAM
Burst of 4
IDT71P73204
IDT71P73104
IDT71P73804
IDT71P73604
Features
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)
Common Read and Write Data Port
Dual Echo Clock Output
4-Word Burst on all SRAM accesses
MultiplexedAddress Bus
- One Read or One Write request per two clock
cycles.
DDR (Double Data Rate) Data Bus
- Four word bursts data per two clock cycles
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70
ohms
1.8V Core Voltage (VDD)
JTAG Interface
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
Description
The IDT DDRIITM Burst of four SRAMs are high-speed synchro-
nous memories with a double-data-rate (DDR), bidirectional data port.
This scheme allows maximization on the bandwidth on the data bus by
passing two data items per clock cycle. The address bus operates at
less than single data rate speeds,allowing the user to fan out addresses
and ease system design while maintaining maximum performance on
data transfers.
The DDRII has scalable output impedance on its data output bus
and echo clocks, allowing the user to tune the bus for low noise and high
performance.
All interfaces of the DDRII SRAM are HSTL, allowing speeds
beyond SRAM devices that use any form of TTL interface. The inter-
face can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
Functional Block Diagram
DATA
REG
(Note2)
SA
SA0
SA1
ADD
REG
(Note2)
LD
RW
BWx
(Note3)
CTRL
LOGIC
(Note1)
WRITE DRIVER
18M
MEMORY
ARRAY
(Note4)
(Note4)
(Note1) DQ
K CLK
K GEN
C SELECT OUTPUT CONTROL
C
CQ
CQ
Notes
6431 drw 16
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 19 address signal lines for x8 and x9, 20 address signal lines for x18, and 19 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
JULY 2005
1
©2005 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
DSC-6431/00
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IDT71P73204 pdf
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Pin Configuration IDT71P73204 (2M x 8)
1 2 3 4 5 6 7 8 9 10 11
A
CQ
VSS/
SA (2)
SA
R/W NW1
K
NC
LD
SA
VSS/
SA (1)
CQ
B NC NC NC SA NC K NW0 SA NC NC DQ3
C NC NC NC VSS SA NC SA VSS NC NC NC
D NC NC NC VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ
NC
NC
NC
G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ
NC
DQ1 NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ
NC
NC
NC
L
NC DQ6 NC VDDQ VSS VSS VSS VDDQ NC
NC DQ0
M NC NC NC VSS VSS VSS VSS VSS NC NC NC
N NC NC NC VSS SA SA SA VSS NC NC NC
P NC NC DQ7 SA SA C SA SA NC NC NC
R
TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
165-ball FBGA Pinout
TOP VIEW
6431 tbl 12
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.542
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IDT71P73204 arduino
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Absolute Maximum Ratings(1)(2)
Symbol
Rating
Value
Unit
Capacitance (TA = +25°C, f = 1.0MHz)(1)
Symbol
Parameter
Conditions Max. Unit
VTERM
VTERM
VTERM
VTERM
Supply Voltage on VDD with
Respect to GND
–0.5 to +2.9
Supply Voltage on VDDQ with
Respect to GND
–0.5 to VDD+0.3
Voltage on Input terminals with
respect to GND
–0.5 to VDD+0.3
Voltage on Input, Output and I/O
terminals with respect to GND
–0.5 to VDDQ+0.3
V
V
V
V
CIN Input Capacitance
5 pF
CCLK Clock Input Capacitance
VDD = 1.8V
6
pF
CO Output Capacitance
VDDQ = 1.5V 7 pF
CDQ DQ I/O Capacitance
7 pF
NOTE:
6431 tbl 06
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
TBIAS Temperature Under Bias
–55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
IOUT Continuous Current into Outputs + 20 mA
NOTES:
6431 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationisnotimplied.Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDDQ must not exceed VDD during normal operation.
Recommended DC Operating and
Temperature Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VDD Power Supply Voltage 1.7
1.8 1.9 V
VDDQ I/O Supply Voltage 1.4 1.5 1.9 V
VSS Ground
0 0 0V
VREF
Input Reference
Voltage
0.68 VDDQ/2 0.95 V
TA Ambient Temperature (1) 0
25 70 oc
NOTE:
6431 tbl 04
1. During production testing, the case temperature equals the ambient
temperature.
61.412
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