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PDF NCP1592 Data sheet ( Hoja de datos )
| Número de pieza | NCP1592 | |
| Descripción | Synchronous Buck PWM Switcher | |
| Fabricantes | ON Semiconductor | |
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NCP1592
3 V to 6 V Input, 6 A Output
Synchronous Buck PWM
Switcher with Integrated
FETs
NCP1592 is a low input voltage 6 A synchronous buck converter
that integrates both 30 mW high side and low side MOSFETs.
NCP1592 is designed for space sensitive and high efficiency
applications. The main features include: a high performance voltage
error amplifier; an under−voltage−lockout circuit to prevent start−up
until the input voltage reaches 3 V; an internally or externally
programmable soft−start circuit to limit inrush currents; and a power
good output monitor signal. NCP1592 is available in thermally
enhanced 28−pin TSSOP package.
http://onsemi.com
MARKING
DIAGRAM
TSSOP−28 EP
CASE 948BG
1592G
ALYW
Features
• 30 mW, 12 A Peak MOSFET Switches for High to Efficiency at 6 A
Continuous Output Source or Sink Current
• Adjustable Output Voltage Down to 0.891 V With 1.0% Accuracy
• Wide PWM Frequency: Fixed 350 kHz, 550 kHz or Adjustable
280 kHz to 700 kHz
• Synchronizable to 700 kHz
• Load Protected by Peak Current Limit and Thermal Shutdown
• Integrated Solution Reduces Board Area and Component Count
• This is a Pb−Free Device
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
Application
• Low−Voltage, High−Density Distributed Power Systems
• High Performance Point of Load Regulation for DSPs, FPGAs,
ASICs and Microprocessors
• Broadband, Networking and Optical Communications Infrastructure
• Portable Computing/Notebook PCs
Input
VIN PH
NCP1592
BOOT
Output
PGND
VI = 5 V,
VO = 3.3 V
LOAD CURRENT (A)
Figure 1. Efficiency at 350 kHz
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
VBIAS
VSENSE
AGND COMP
Figure 2. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2012
July, 2012 − Rev. 1
1
Publication Order Number:
NCP1592/D
Free Datasheet http://www.datasheet4u.com/
1 page  
NCP1592
ELECTRICAL CHARACTERISTICS Over operating free−air temperature range unless otherwise noted
Parameter
Symbol
Test Conditions
Min Typ
Power Supply, VIN
VIN Operation Voltage
Quiescent Current
VIN
I(QSW 350)
Fs = 350 kHz, SYNC ≤ 0.8 V, RT
open, PH pin open
3
3.5
I(QSW 550)
Fs = 550 kHz, SYNC ≥ 2.5 V, RT
open, PH pin open
4.0
UNDERVOLTAGE LOCKOUT
I(QSD)
Shutdown, SS / ENA = 0 V
1
Start Threshold
UVLOR
2.95
Stop Threshold
UVLOF
2.7 2.8
UVLO Hysteresis
UVLOHYST
110 160
Rising and falling edge deglitch
(Note 5)
UVLORTD
2.5
BIAS VOLTAGE
Output Voltage
Output Current (Note 6)
CUMULATIVE REFERENCE
Vbias
IVbias
IVbias = 0
2.7 2.8
Reference Voltage Accuracy
REGULATION
Vref
0.882 0.891
Line regulation (Notes 6 and 7)
Load regulation (Notes 5 and 7)
IL = 3 A, Fs = 350 kHz, TJ = 85°C
IL = 3 A, Fs = 550 kHz, TJ = 85°C
IL = 0 A to 6 A, Fs = 350 kHz,
TJ = 85°C
OSCILLATOR
IL = 0 A to 6 A, fs = 550 kHz,
TJ = 85°C
Internally set
Externally set
FREQSYNC_LOW
FREQ_HIGH
FREQ180RT
SYNC ≤ 0.8 V, RT open
SYNC ≥ 2.5 V, RT open
RT = 180 kW (1% resistor to
AGND) (Note 5)
280 350
440 550
252 280
FREQ100RT
RT = 100 kW (1% resistor to
AGND)
460 500
FREQ68RT
RT = 68 kW (1% resistor to
AGND) (Note 5)
663 700
High level threshold
SYNCH
2.5
Low level threshold
SYNCL
External synchronization pulse
duration (Note 5)
SYNCMIN
50
Frequency range (Note 5)
SYNCFREQ
330
Ramp valley (Note 5)
RAMP_Bot
0.441
Peak−to−peak ramp amplitude
(Note 5)
RAMP_AMP
1
Minimum controllable on time
(Note 5)
MIN_COT
Maximum duty cycle
DMAX
90%
5. Guaranteed by design.
6. Static resistive loads only.
7. Specified by the circuit used in Figure 14.
8. Matched MOSFETs low−side RDS(on) production tested, high−side RDS(on) specified by design.
MAX
6
11.2
16
1.4
3.0
2.90
100
0.900
0.04
0.04
0.03
0.03
420
660
308
540
762
0.8
700
200
Unit
V
mA
mA
mA
V
V
mV
ms
V
mA
V
%/V
%/A
kHz
kHz
V
V
ns
kHz
V
V
ns
http://onsemi.com
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
NCP1592
Figure 15. Recommended Land Pattern For 28−Pin PowerPAD
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide an adequate heat dissipating area. A
3−inch by 3−inch plane of 1 copper is recommended, though
not mandatory, depending on ambient temperature and
airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD must be
connected to the largest area available. Additional areas on
the top or bottom layers also help dissipate heat, and any area
available must be used when 6 A or greater operation is
desired. Connection from the exposed area of the
PowerPAD to the analog ground
plane layer must be made using 0.013 inch diameter vias
to avoid solder wicking through the vias. Eight vias must be
in the PowerPAD area with four additional vias located
under the device package. The size of the vias under the
package, but not in the exposed thermal pad area, can be
increased to 0.018. Additional vias beyond the twelve
recommended that enhance thermal performance must be
included in areas not under the device package.
http://onsemi.com
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet NCP1592.PDF ] | |
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