PDF K4H510838J Data sheet ( Hoja de datos )

Número de pieza	K4H510838J
Descripción	512Mb J-die DDR SDRAM
Fabricantes	Samsung
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Hay una vista previa y un enlace de descarga de K4H510838J (archivo pdf) en la parte inferior de esta página. Total 27 Páginas
No Preview Available ! Rev. 1.11, Aug. 2011 K4H510438J K4H510838J K4H511638J 512Mb J-die DDR SDRAM 60FBGA & 66TSOP-(II) with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2011 Samsung Electronics Co., Ltd. All rights reserved. -1- Free Datasheet http://www.datasheet4u.com/ 1 page K4H510438J K4H510838J K4H511638J datasheet Rev. 1.11 DDR SDRAM 4. Pin / Ball Description 4.1 Pin Description 32Mb x 16 64Mb x 8 128Mb x 4 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 66 2 65 3 64 4 63 5 62 6 61 7 60 8 59 9 58 10 66Pin TSOPII 57 11 (400mil x 875mil) 56 12 (0.65mm Pin Pitch) 55 13 54 14 15 16 Bank Address BA0~BA1 53 52 51 17 50 18 19 Auto Precharge A10 49 48 20 47 21 46 22 45 23 44 24 43 25 42 26 41 27 40 28 39 29 38 30 37 31 36 32 35 33 34 512Mb TSOP-II Package Pinout VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS Organization 128Mx4 64Mx8 32Mx16 Row Address A0~A12 A0~A12 A0~A12 Column Address A0~A9, A11, A12 A0-A9, A11 A0-A9 DM is internally loaded to match DQ and DQS identically. Row & Column address configuration -5- Free Datasheet http://www.datasheet4u.com/ 5 Page K4H510438J K4H510838J K4H511638J datasheet Rev. 1.11 DDR SDRAM 7. Command Truth Table Register Register Refresh COMMAND Extended MRS Mode Register Set Auto Refresh Self Refresh Entry Exit Bank Active & Row Addr. Read & Column Address Auto Precharge Disable Auto Precharge Enable Write & Column Address Auto Precharge Disable Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Active Power Down Entry Exit Precharge Power Down Mode Entry Exit DM(UDM/LDM for x16 only) No operation (NOP) : Not defined CKEn-1 CKEn CS RAS CAS H XLL L H XLL L H H LL L L LH H LH HX X H XLL H H X LH L H X LH L H X LH H H XLL H HX X HL LV V L HXX X HX X HL LH H HX X LH LV V HX HX X HX LH H (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) WE BA0,1 A10/AP A0 ~ A9, A11 ~ A12 NOTE L OP CODE 1, 2 L OP CODE 1, 2 3 HX 3 H3 X X3 HV Row Address HV L H Column Address 4 4 LV L H Column Address 4 4, 6 LX7 V L X L H X 5 X VX X X H X X V X8 X9 X H9 NOTE : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. - 11 - Free Datasheet http://w 11 Page

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