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PDF 82806AA Data sheet ( Hoja de datos )

Número de pieza 82806AA
Descripción PCI 64 Hub
Fabricantes Intel 
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R
Intel® 82806AA PCI 64 Hub (P64H)
Datasheet
March 2001
Document Number: 298025-002
Free Datasheet http://www.datasheet4u.com/

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82806AA pdf
Intel® 82806AA PCI 64 Hub (P64H)
R
3.4.3.3. Posted Write Transactions (Data Parity) ............................................ 71
3.4.3.4. I/O Write Transaction ......................................................................... 71
3.4.4. Master Aborts ................................................................................................... 72
3.4.4.1. Non-Posted Transactions ................................................................... 72
3.4.4.2. Posted Write Transactions ................................................................. 73
3.4.4.3. Exclusive Access Master-Abort .......................................................... 73
3.4.5. System Error (SERR#) Reporting..................................................................... 73
3.4.5.1. PCI SERR# Pin Assertion................................................................... 73
3.4.5.2. Other System Error............................................................................. 73
3.5. Advanced Interrupt Controller (APIC)............................................................................ 74
3.5.1. Interrupt Handling ............................................................................................. 74
3.5.2. Interrupt Mapping.............................................................................................. 74
3.5.3. APIC Bus Functional Description...................................................................... 74
3.5.3.1. Physical Characteristics of APIC ........................................................ 74
3.5.3.2. APIC Bus Arbitration........................................................................... 74
3.5.3.3. Bus Message Formats........................................................................ 75
3.5.3.3.1. EOI Message For Level Triggered Interrupts................... 76
3.5.3.3.2. Short Message ................................................................. 77
3.5.3.3.3. Lowest Priority Message Without Focus Processor (FP). 78
3.5.3.3.4. Remote Read Message ................................................... 80
3.5.4. Boot Interrupt .................................................................................................... 81
3.6. Clocking and Reset ....................................................................................................... 82
3.6.1. Clocking ............................................................................................................ 82
3.6.2. Reset ............................................................................................................ 82
3.6.2.1. Reset In (RSTIN#) .............................................................................. 82
3.6.2.2. Secondary Bus Reset ......................................................................... 83
3.7. Reference Power Voltage.............................................................................................. 83
3.7.1. 5V Reference Requirements ............................................................................ 83
4. Ballout and Package Information ............................................................................................... 85
4.1. P64H Ball Assignment................................................................................................... 85
4.2. Package Specification ................................................................................................... 90
5. Testability ................................................................................................................................... 93
5.1. Tri-State Mode............................................................................................................... 93
5.2. NAND Tree Mode.......................................................................................................... 93
Datasheet
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82806AA arduino
Intel® 82806AA PCI 64 Hub (P64H)
R
1. Signal Description
This section provides a detailed description of P64H signals. The signals are arranged in functional
groups according to their associated interface. The states of all of the signals during reset are provided in
Clocking and Reset, Section 3.6
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the
signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when
at the high voltage level.
The following notations are used to describe the signal type:
I Input pin
O Output pin
OD Open Drain Output pin.
I/OD Input / Open Drain Output pin.
I/O Bi-directional Input/Output pin
1.1. Hub Interface to the Host Controller
Table 1. Hub Interface Signals
Name
Type
HLB_STB[1:0]
HLB_STB[1:0]#
I/O
CMOS
I/O
CMOS
HLBRCOMP
I/O
CMOS
HLB[19:0]
I/O
CMOS
Description
Hub Interface Packet Strobe: This signal is a part of the differential strobe pair.
This signal is used to transmit or receive the data on the hub interface.
Hub Interface Packet Strobe Complement: This signal is a part of the
differential strobe pair. This signal is used to transmit or receive the data on the
hub interface.
Hub Interface B Resistive Compensation: This signal is used to calibrate the
hub interface B I/O buffers. The P64H only supports RCOMP. This signal must be
tied to ground via a 30 pull-down resistor.
Hub Interface Signals.
Datasheet
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