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PDF ACPL-38JT Data sheet ( Hoja de datos )
| Número de pieza | ACPL-38JT | |
| Descripción | Automotive Gate Drive Optocoupler | |
| Fabricantes | AVAGO | |
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ACPL-38JT
Automotive Gate Drive Optocoupler with R2Coupler™ Isolation,
2.5 Amp Output Current, Integrated Desaturation (VCE) Detection
and Fault Status Feedback
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Avago’s automotive 2.5 Amp Gate Drive Optocoupler with
Integrated Desaturation (VCE) Detection and Fault Status
Feedback makes automotive IGBT VCE fault protection
compact, affordable, and easy-to-implement while satis-
fying automotive AEC-Q100 Grade 1 semiconductor re-
quirement.
Avago R2Coupler isolation products provide the rein-
forced insulation and reliability needed for critical in auto-
motive and high temperature industrial applications
Functional Diagram
VLED1+ VLED1–
78
VIN+ 2
VIN– 3
LED1
D
R
I
V
E
R
VCC1
RESET
FAULT
4
5
6 FAULT
SHIELD
LED2
GND1 1
SHIELD
UVLO
DESAT
13
VCC2
11 VC
10
VOUT
14 DESAT
9, 12
VEE
16 VE
15 VLED2+
2.5 A maximum peak output current
Drive IGBTs up to IC = 150 A, VCE = 1200 V
Optically isolated, FAULT status feedback
SO-16 package
CMOS/TTL compatible
500 ns max. switching speeds
“Soft” IGBT turn-off
Integrated fail-safe IGBT protection
– Desat (VCE) detection
– Under Voltage Lock-Out protection (UVLO) with
hysteresis
User configurable: inverting, noninverting, auto-reset,
auto-shutdown
Wide operating VCC range: 15 to 30 Volts
-40°C to +125°C operating temperature range
15 kV/s min. Common Mode Rejection (CMR) at VCM =
1500 V
Qualified to AEC-Q100 Grade 1 Test Guidelines
Regulatory approvals:
– UL1577, CSA
– IEC/EN/DIN EN 60747-5-5
Applications
Figure 1. ACPL-38JT Functional Diagram
Automotive Isolated IGBT/MOSFET Inverter gate drive
Automotive DC-DC Converter
AC and brushless dc motor drives
Industrial inverters for power supplies and motor
controls
Un-interruptible Power Supplies
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Free Datasheet http://w
1 page  
Package Pin Out
1 GND1
2 VIN+
3 VIN
4 VCC1
5 RESET
6 FAULT
7 VLED1+
8 VLED1
VE 16
VLED2+ 15
DESAT 14
VCC2 13
VEE 12
VC 11
VOUT 10
VEE 9
Pin Descriptions
Symbol
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
Description
Noninverting gate drive voltage output (VOUT)
control input.
Inverting gate drive voltage output (VOUT)
control input.
Positive input supply voltage. (4.5 V to 5.5 V)
Symbol
VE
VLED2+
DESAT
Input Ground.
FAULT reset input. A logic low input for at least
0.1 s, asynchronously resets FAULT output high
and enables VIN. Synchronous control of RESET
relative to VIN is required. RESET is not affected
by UVLO. Asserting RESET while VOUT is high does
not affect VOUT.
Fault output. FAULT changes from a high impedance
state to a logic low output within 5 s of the voltage
on the DESAT pin exceeding an internal reference
voltage of 7V. FAULT output remains low until RESET
is brought low. FAULT output is an open collector
which allows the FAULT outputs from all HCPL-316Js
in a circuit to be connected together in a “wired OR”
forming a single fault bus for interfacing directly to
the micro-controller.
LED 1 anode. This pin must be left unconnected
for guaranteed data sheet performance.
(For optical coupling testing only.)
LED 1 cathode. This pin must be connected to
ground.
VCC2
VC
VOUT
VEE
Description
Common (IGBT emitter) output supply voltage.
LED 2 anode. This pin must be left unconnected
for guaranteed data sheet performance.
(For optical coupling testing only.)
Desaturation voltage input. When the voltage
on DESAT exceeds an internal reference voltage
of 7V while the IGBT is on, FAULT output is changed
from a high impedance state to a logic low state
within 5 s. See Note 25.
Positive output supply voltage.
Collector of output pull-up triple-darlington
transistor. It is connected to VCC2 directly or through
a resistor to limit output turn-on current.
Gate drive voltage output.
Output supply voltage.
5
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Notes:
1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 Vrms for 1 second.
2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-5 Insulation
Characteristics Table.
3. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 12 shorted together.
4. In order to achieve the absolute maximum power dissipation specified, pins 1, 9, and 12 require ground plane connections and may require
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power
dissipation does not require de-rating.
5. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO
peak minimum = 2.0 A. See Applications section for additional details on IOH peak. De-rate linearly from 3.0 A at +25°C to 2.5 A at +125°C. This
compensates for increased IOPEAK due to changes in VOL over temperature.
6. This supply is optional. Required only when negative gate drive is implemented.
7. Maximum pulse width = 50 s, maximum duty cycle = 0.5%.
8. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
9. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+
threshold of 13.5 V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will
approach VCC as IOH approaches zero units.
10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
11. Once VOUT of the ACPL-38JT is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the ACPL-38JT will be the primary source of
IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- < 12.4 V. Thus, the
DESAT detection and UVLO features of the ACPL-38JT work in conjunction to ensure constant IGBT protection.
12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details.
13. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE.
14. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 - VE.
15. This load condition approximates the gate load of a 1200 V/75A IGBT.
16. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit.
17. As measured from VIN+, VIN- to VOUT.
18. The difference between tPHL and tPLH between any two ACPL-38JT parts under the same test conditions.
19. Supply Voltage Dependent.
20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
21. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low.
22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 μs is the guaranteed
minimum FAULT signal pulse width when the ACPL-38JT is configured for Auto-Reset. See the Auto-Reset section in the applications notes at the
end of this data sheet for further details.
23. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 3K pull-up resistor is needed in fault detection mode.
24. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V).
25. Does not include LED2 current during fault or blanking capacitor discharge current.
26. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 A
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.
27. The recommended output pull-down resistor between VOUT and VEE does not contribute any output current when VOUT = VEE.
28. In most applications VCC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control of the
IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that Vin+ remains low until VCC1 reaches the proper operating
voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down.
11
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