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PDF NTP-8230 Data sheet ( Hoja de datos )

Número de pieza NTP-8230
Descripción Power Driver Integrated Full Digital Audio Amplifier
Fabricantes NeoFidelity 
Logotipo NeoFidelity Logotipo



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No Preview Available ! NTP-8230 Hoja de datos, Descripción, Manual

Power Driver Integrated Full Digital Audio Amplifier
NTP-8230
NTP-8230
High Performance, High Fidelity Power
Driver Integrated Full Digital Audio Amplifier
Datasheet
Revision 0.1
Copyright NeoFidelity, Inc.
Document Number: DS8230 draft ver. 0.1
Page 1
2011-01-11
Free Datasheet http://www.datasheet4u.com/

1 page




NTP-8230 pdf
Power Driver Integrated Full Digital Audio Amplifier
NTP-8230
3. PIN DESCRIPTIONS
PIN NAME TYPE
DESCRIPTION
1 AVDD_PLL
P Regulator output for PLL analog block, 1.8V
2 DVDD_PLL
P Regulator output for PLL digital block, 1.8V
3 LF I/O External PLL loop filter
4 GND
P This pin should be connected to Ground
5 SDATA
I I2S serial data input
6 WCK I/O I2S word clock
7 BCK I/O I2S bit clock
8 SDA I/O I2C data
9 SCL
I I2C clock
10 DVDD
P Regulator output for Core block, 1.8V
11 /FAULT
I Input from external power device
12 PWM_MASK_2 O External power device on/off control to protect
13
S_WOOFER_A/
MONITOR_0
O
Monitoring signal out from processor block
14
S_WOOFER_B/
MONITOR_1
O
Monitoring signal out from processor block
15 HP_L
O Left audio channel Headphone signal
16 HP_R
O Right audio channel Headphone signal
17 HP_MUTE
O External Headphone mute signal
18 BST2B
P Bootstrap supply, external capacitor to OUT2B is required
19 PGND2B
P Ground
20 OUT2B
O Power stage PWM output 2B
21 OUT2B
O Power stage PWM output 2B
22 PVDD2
P Power supply for PWM Power stage 2A, 2B
23 PVDD2
P Power supply for PWM Power stage 2A, 2B
24 PVDD2
P Power supply for PWM Power stage 2A, 2B
25 OUT2A
O Power stage PWM output 2A
26 OUT2A
O Power stage PWM output 2A
27 PGND2A
P Ground
28 BST2A
P Bootstrap supply, external capacitor to OUT2A is required
29 VDR2
P Gate drive voltage regulator decoupling pin, capacitor to GND is required
30 AGND
P Ground
31 VCC5
P Logic voltage decoupling pin, capacitor to GND is required
32 VDR1
P Gate drive voltage regulator decoupling pin, capacitor to GND is required
33 BST1B
P Bootstrap supply, external capacitor to OUT1B is required
34 PGND1B
P Ground
35 OUT1B
O Power stage PWM output 1B
36 OUT1B
O Power stage PWM output 1B
37 PVDD1
38 PVDD1
39 PVDD1
P Power supply for PWM Power stage 1A, 1B
P Power supply for PWM Power stage 1A, 1B
P Power supply for PWM Power stage 1A, 1B
40 OUT1A
O Power stage PWM output 1A
Copyright NeoFidelity, Inc.
Document Number: DS8230 draft ver. 0.1
Page 5
2011-01-11
Free Datasheet http://www.datasheet4u.com/

5 Page





NTP-8230 arduino
Power Driver Integrated Full Digital Audio Amplifier
NTP-8230
5.1.1. Writing Operation
When last 8th bit of the 1st byte is set to low state, the writing operation of I2C bus begins. The NTP-
8230 supports 3 kind of writing operations which presented on Figure 6
The type presented on Figure 6-(a) is single byte write operation. “Sub address” on 2nd byte means
the internal register address of the NTP-8230. The “Data” on 3rd byte will be written into the internal
register address on “Sub address”. If stop condition is not generated, writing “data” on specific “sub
address” can be repeated like Figure 6-(b). “Data #n” will be written on “sub address #n”.
The type presented on Figure 6-(c) is burst byte write operation under address auto increment mode.
The AIF is the address Auto Increment Flag which is 1st bit of 2nd byte of I2C packet. On SDA, if AIF
is set to high state, the NTP-8230 starts auto incrementing the address with respect to given sub
addressand host send write data continuously over SDA. In AIF mode, access to the register
addresses 0x3B~0x49, 0x4F and 0x5E are automatically skipped.
(a)
S Slave address W A AIF Sub Address
(b)
A
Data
AP
S Slave address W A AIF Sub Address #1
(c)
A
Data #1
A AIF Sub Address #2 A
Data #2
A
P
S Slave address W A AIF Sub Address #1 A
Data #1
A
Data #n
AP
Figure 6. Single Byte Write Mode Sequence
Figure 7-(a), Figure 7-(b), and Figure 7-(c) represent 4 byte writing operations. Coefficient Mode
Register address 0x00~0x6B are used to configure Bi-Quad filter coefficients, Low Shelf BQ filter
coefficients, Loudness gains and DRC clip down gain. The data size of these coefficients and gains is
4 byte for each. The difference between 4byte writing operation and single byte writing operation is
only the size of transferring data. So, after sending “Sub address”, 4 sequential bytes must be
transferred from the MSB(most significant byte) to the LSB(least significant byte) sequence.
The type presented on Figure 7-(c) is quad byte write operation under address auto increment mode,
AIF function. Please compare the data transfer size between Figure 6 and Figure 7.
(a)
S Slave address W A AIF Sub Address
(b)
A Data (Byte #4)
A Data (Byte #3)
A Data (Byte #2) A Data (Byte #1)
AP
S
Slave address W A AIF Sub Address #1
A
Data (Byte #4)
A Data (Byte #3)
A Data (Byte #2) A Data (Byte #1)
A
AIF Sub Address #n
A Data #n (Byte #4)
A Data #n (Byte #3)
A Data #n (Byte #2) A Data #n (Byte #1)
AP
(c)
S Slave address W A AIF Sub Address
A Data (Byte #4)
A Data (Byte #3)
A Data (Byte #2) A Data (Byte #1)
A
A Data #n-1 (Byte #1)
A Data #n (Byte #4)
Data #n (Byte #3)
Data #n (Byte #2) A Data #n (Byte #1)
Figure 7. Quad Byte Write Mode Sequences
AP
In write operation, the register 0x7E value needs to be set first for performing the configuration of the
registers belong to all channels. The 0x7E register also support to configuring byte writes operation
and word i.e. 4 byte writes operation.
If 0x7E register is configure to 0x00, it support byte write operation and for word i.e. 4 byte write
operation for each channel it needs to configure as 0x01 for channel 1, 0x02 for channel 2, 0x04 for
Copyright NeoFidelity, Inc.
Page 11
Document Number: DS8230 draft ver. 0.1
2011-01-11
Free Datasheet http://www.datasheet4u.com/

11 Page







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