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PDF 24LC64F Data sheet ( Hoja de datos )
| Número de pieza | 24LC64F | |
| Descripción | EEPROM | |
| Fabricantes | Microchip | |
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24AA64F/24LC64F/24FC64F
64K I2C™ Serial EEPROM with Quarter-Array Write-Protect
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
24AA64F
1.7-5.5
400 kHz(1)
24LC64F
24FC64F
2.5-5.5
1.7-5.5
400 kHz
1 MHz(2)
Note 1: 100 kHz for VCC <2.5V.
2: 400 kHz for VCC <2.5V.
Temp.
Ranges
I
I, E
I
Features:
• Single-Supply with Operation down to 1.7V for
24AA64F/24FC64F Devices, 2.5V for 24LC64F
Devices
• Low-Power CMOS Technology:
- Read current 400 A, max.
- Standby current 1 A, max. (I-temp)
• 2-Wire Serial Interface, I2C™ Compatible
• Packages with Three Address Pins are
Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 5 ms, typical
• Self-timed Erase/Write Cycle
• 32-Byte Page Write Buffer
• Hardware Write-Protect for 1/4 Array
(1800h-1FFFh)
• ESD Protection > 4,000V
• More than One Million Erase/Write Cycles
• Data Retention > 200 Years
• Factory Programming Available
• Packages include 8-Lead PDIP, SOIC, TSSOP,
MSOP, TDFN, 5-Lead SOT-23
• Pb-Free and RoHS Compliant
Package Types
PDIP/MSOP/SOIC/TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
SCL
VSS
SDA
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA64F/24LC64F/
24FC64F (24XX64F*) is a 64 Kbit Electrically Erasable
PROM. The device is organized as a single block of
8K x 8-bit memory with a 2-wire serial interface. Low-
voltage design permits operation down to 1.7V, with
standby and read currents of only 1 A and 400 A,
respectively. It has been developed for advanced, low-
power applications such as personal communications
or data acquisition. The 24XX64F also has a page
write capability for up to 32 bytes of data. Functional
address lines allow up to eight devices on the same
bus, for up to 512 Kbits address space. The 24XX64F
is available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, TDFN and MSOP packages. The
24XX64F is also available in the 5-lead SOT-23
package.
Block Diagram
A0 A1 A2 WP
HV
Generator
I/O
Control
Logic
I/O
SCL
SDA
VCC
VSS
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
YDEC
Sense Amp.
R/W Control
SOT-23
15
WP
2
3 4 VCC
TDFN
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
*24XX64F is used in this document as a generic part number for the 24AA64F/24LC64F/24FC64F devices.
2009-2012 Microchip Technology Inc.
DS22154B-page 1
1 page  
24AA64F/24LC64F/24FC64F
2.0 PIN DESCRIPTIONS
TABLE 2-1:
Name
A0
A1
A2
VSS
SDA
SCL
WP
VCC
PIN FUNCTION TABLE
PDIP
SOIC TSSOP
111
222
333
444
555
666
777
888
TDFN
1
2
3
4
5
6
7
8
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX64F for
multiple device operation. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed. Address
pins are not available in the SOT-23 package.
2.2 Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 k for 100 kHz, 2 kfor 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
The descriptions of the pins are listed in Table 2-1.
MSOP
1
2
3
4
5
6
7
8
SOT-23
—
—
—
2
3
1
5
4
Description
Chip Address Input
Chip Address Input
Chip Address Input
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.7V to 5.5V Power Supply
2.3 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
from and to the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited for upper 1/4 of the array
(1800h-1FFFh), but read operations are not affected.
3.0 FUNCTIONAL DESCRIPTION
The 24XX64F supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX64F works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
2009-2012 Microchip Technology Inc.
DS22154B-page 5
5 Page 
24AA64F/24LC64F/24FC64F
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX64F contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24XX64F issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX64F discontinues transmission (Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To
perform this type of read operation, the word address
must first be set. This is accomplished by sending
the word address to the 24XX64F as part of a write
operation (R/W bit set to ‘0’). Once the word address
is sent, the master generates a Start condition
following the acknowledge.
FIGURE 8-1:
CURRENT ADDRESS READ
S
Bus Activity T Control
Master
A
R
Byte
T
SDA Line
S
Bus Activity
This terminates the write operation, but not before
the internal Address Pointer is set. The master then
issues the control byte again, but with the R/W bit set
to a one. The 24XX64F will then issue an acknowl-
edge and transmit the 8-bit data word. The master
will not acknowledge the transfer, but does generate
a Stop condition, which causes the 24XX64F to
discontinue transmission (Figure 8-2). After a
random Read command, the internal address coun-
ter will point to the address location following the one
that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as
random reads, except that once the 24XX64F transmits
the first data byte, the master issues an acknowledge as
opposed to the Stop condition used in a random read.
This acknowledge directs the 24XX64F to transmit the
next sequentially-addressed 8-bit word (Figure 8-3).
Following the final byte being transmitted to the master,
the master will NOT generate an acknowledge, but will
generate a Stop condition. To provide sequential reads,
the 24XX64F contains an internal Address Pointer
which is incremented by one at the completion of each
operation. This Address Pointer allows the entire
memory contents to be serially read during one opera-
tion. The internal Address Pointer will automatically roll
over from address 1FFF to address 0000 if the master
acknowledges the byte received from the array address
1FFF.
Data (n)
A
C
K
S
T
O
P
P
N
O
A
C
K
2009-2012 Microchip Technology Inc.
DS22154B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 24LC64F.PDF ] | |
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