PDF DMP2018LFK Data sheet ( Hoja de datos )

Número de pieza	DMP2018LFK
Descripción	P-CHANNEL ENHANCEMENT MODE MOSFET
Fabricantes	Diodes
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No Preview Available ! DMP2018LFK P-CHANNEL ENHANCEMENT MODE MOSFET Product Summary V(BR)DSS -20V RDS(on)max 16mΩ @ VGS = -4.5V 25mΩ @ VGS = -2.0V ID TA = 25°C -12.8A -10A Description and Applications This new generation MOSFET has been designed to minimize the on- state resistance (RDS(on)) and yet maintain superior switching performance, making it ideal for high efficiency power management applications. • DC-DC Converters • Power management functions • Notebook PC Applications • Portable Equipment Applications Features and Benefits • Low On-Resistance • Low Input Capacitance • Low Input/Output Leakage • ESD Protected Gate up to 2kV • Lead Free by Design, RoHS Compliant (Note 1) • "Green" Device (Note 2) • Qualified to AEC-Q101 Standards for High Reliability Mechanical Data • Case: U-DFN2523-6 • Case Material: Molded Plastic, "Green" Molding Compound. UL Flammability Classification Rating 94V-0 • Moisture Sensitivity: Level 1 per J-STD-020 • Terminals: Finish ⎯ NiPdAu over Copper leadframe. Solderable per MIL-STD-202, Method 208 • Weight: 0.008 grams (approximate) U-DFN2523-6 Pin 1 Pin 1, 2 = Source Pin 3 = Gate Pin 4, 5, 6 = Drain ESD PROTECTED TO 2kV Bottom View Drain Gate Gate Protection Source Diode Equivalent Circuit Ordering Information (Note 3) Notes: Part Number DMP2018LFK-7 DMP2018LFK-13 Case U-DFN2523-6 U-DFN2523-6 Packaging 3,000 / Tape & Reel 10,000 / Tape & Reel 1. EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. No purposely added lead. Halogen and Antimony free. 2. Diodes Inc.'s "Green" policy can be found on our website at http://www.diodes.com. 3. For packaging details, go to our website at http://www.diodes.com. Marking Information P8 = Product Type Marking Code P8 YM = Date Code Marking Y = Year (ex: Y = 2011) M = Month (ex: 9 = September) Date Code Key Year Code Month Code 2011 Y Jan Feb 12 DMP2018LFK Document number: DS35357 Rev. 5 - 2 2012 Z Mar 3 2013 A Apr May 45 2014 B Jun Jul 67 1 of 7 www.diodes.com 2015 C Aug 8 Sep 9 2016 D Oct O 2017 E Nov Dec ND March 2012 Free Datash©eeDtihotdtpe:s//Iwncwowrp.doartaatsehdeet4u.com/ 1 page DMP2018LFK 10,000 Ciss 1,000 Coss Crss f = 1MHz 100,000 10,000 1,000 100 10 TA = 150°C TA = 125°C TA = 85°C 100 0 5 10 15 -VDS, DRAIN-SOURCE VOLTAGE (V) Fig. 9 Typical Total Capacitance 20 10 1 TA = 25°C 0 4 8 12 16 -VDS, DRAIN-SOURCE VOLTAGE (V) Fig. 10 Typical Leakage Current vs. Drain-Source Voltage 100 RDS(on) Limited 20 8 VDS = -16V ID = -7.2A 6 4 2 0 0 20 40 60 80 100 120 Qg, TOTAL GATE CHARGE (nC) Fig. 11 Gate-Charge Characteristics 1 D = 0.7 D = 0.5 D = 0.3 10 DC PW = 10s PW = 1s 1 PW = 100ms PW = 10ms PW = 1ms PW = 100µs 0.1 PW = 10µs TJ(max) = 150°C TA = 25°C Single Pulse 0.01 0.1 1 10 VDS, DRAIN-SOURCE VOLTAGE (V) Fig. 12 Safe Operation Area 100 0.1 D = 0.1 D = 0.05 D = 0.02 0.01 D = 0.01 D = 0.005 D = Single Pulse 0.001 0.00001 0.0001 0.001 D = 0.9 RθJA(t) = r(t) * RθJA RθJA = 61°C/W P(pk) t1 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1/t2 0.01 0.1 1 t1, PULSE DURATION TIME (s) Fig. 13 Transient Thermal Response 10 100 1,000 DMP2018LFK Document number: DS35357 Rev. 5 - 2 5 of 7 www.diodes.com March 2012 Free Datash©eeDt ihotdtpe:s//Iwncwowrp.doartaatsehdeet4u.com/ 5 Page

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