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PDF 24FC256 Data sheet ( Hoja de datos )
| Número de pieza | 24FC256 | |
| Descripción | EEPROM | |
| Fabricantes | Microchip | |
| Logotipo |  |
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24AA256/24LC256/24FC256
256K I2C™ CMOS Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock Temp.
Frequency Ranges
24AA256
1.7-5.5V 400 kHz(1)
24LC256
24FC256
2.5-5.5V
1.7-5.5V
400 kHz
1 MHz(2)
Note 1: 100 kHz for VCC < 2.5V.
2: 400 kHz for VCC < 2.5V.
I, E
I, E
I
Features:
• Single Supply with Operation Down to 1.7V for
24AA256 and 24FC256 Devices, 2.5V for
24LC256 Devices
• Low-Power CMOS Technology:
- Active current 400 uA, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms Max.
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC, DFN,
TDFN, TSSOP and MSOP
• Pb-Free and RoHS Compliant
Package Types
• Temperature Ranges:
- Industrial (I):
- Automotive (E):
-40C to +85C
-40C to +125C
Description:
The Microchip Technology Inc. 24AA256/24LC256/
24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.7V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This device also has a page write capability of up to 64
bytes of data. This device is capable of both random
and sequential reads up to the 256K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 2 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIC, TSSOP, MSOP, DFN and TDFN packages. The
24AA256 is also available in the 8-lead Chip Scale
package.
Block Diagram
A0 A1A2 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
I/O SCL
SDA
VCC
VSS
XDEC
EEPROM
Array
Page Latches
YDEC
Sense Amp.
R/W Control
PDIP/SOIC
TSSOP/MSOP(1)
DFN/TDFN
CS (Chip Scale)(2)
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
Note 1: * Pins A0 and A1 are no connects for the MSOP package only.
Note 2: Available in I-temp, “AA” only.
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
WP
VCC A1 A0
123
45
6 78
SDA SCL VSS
(TOP DOWN VIEW,
BALLS NOT VISIBLE)
A2
*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.
1998-2013 Microchip Technology Inc.
DS20001203T-page 1
Free Datasheet http://www.datasheet4u.com/
1 page  
24AA256/24LC256/24FC256
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name
8-pin
PDIP
8-pin
SOIC
8-pin
TSSOP
A0
A1
(NC)
A2
VSS
SDA
SCL
(NC)
WP
VCC
111
222
———
333
444
555
666
———
777
888
8-pin
MSOP
—
—
1, 2
3
4
5
6
—
7
8
8-pin
DFN/TDFN
1
2
—
3
4
5
6
—
7
8
CS
3
2
—
5
8
6
7
—
4
1
Note: Exposed pad on DFN/TDFN can be connected to VSS or left floating.
Function
User Configurable Chip Select
User Configurable Chip Select
Not Connected
User Configurable Chip Select
Ground
Serial Data
Serial Clock
Not Connected
Write-Protect Input
+1.7V to 5.5V (24AA256)
+2.5V to 5.5V (24LC256)
+1.7V to 5.5V (24FC256)
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX256 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
For the MSOP package only, pins A0 and A1 are not
connected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
3.0 FUNCTIONAL DESCRIPTION
The 24XX256 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX256 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
1998-2013 Microchip Technology Inc.
DS20001203T-page 5
Free Datasheet http://www.datasheet4u.com/
5 Page 
24AA256/24LC256/24FC256
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be resent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 7-1 for
flow diagram.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
YES
Next
Operation
NO
1998-2013 Microchip Technology Inc.
DS20001203T-page 11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 24FC256.PDF ] | |
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