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PDF AD5669R Datasheet ( Hoja de datos )

Número de pieza AD5669R
Descripción (AD5629R / AD5669R) Octal / 12-/16-Bit / I2C / denseDACs
Fabricantes Analog Devices 
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AD5669R datasheet

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AD5669R pdf
Data Sheet
AD5629R/AD5669R
VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE 2
AD5629R
Resolution
Relative Accuracy
Differential Nonlinearity
AD5669R
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
DC Power Supply Rejection
Ratio
DC Crosstalk
(External Reference)
DC Crosstalk
(Internal Reference)
OUTPUT CHARACTERISTICS 3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
AD5629R/AD5669R
Reference Tempco3
Reference Output Impedance
LOGIC INPUTS3
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
A Grade 1
Min Typ Max
12
±0.5 ±4
±0.25
16
±8 ±32
±1
6 19
±2
−0.2 −1
±1
±2.5
±6 ±19
–80
10
5
10
25
10
0 VDD
2
10
0.5
30
4
40 50
0 VDD
14.6
1.247
1.253
±15
7.5
±3
0.8
2
3
B Grade1
Min Typ Max
12
±0.5 ±1
±0.25
16
±8 ±16
±1
6 19
±2
−0.2 −1
±1
±2.5
±6 ±19
–80
10
5
10
25
10
0 VDD
2
10
0.5
30
4
40 50
0 VDD
14.6
1.247
±5
±15
7.5
1.253
±15
±3
0.8
2
3
Unit
Bits
LSB
LSB
Bits
LSB
LSB
mV
µV/°C
% FSR
% FSR
ppm
mV
dB
µV
µV/mA
µV
µV
µV/mA
V
nF
nF
mA
µs
µA
kΩ
V
ppm/°C
kΩ
µA
V
V
pF
Conditions/Comments
See Figure 6
Guaranteed monotonic by design (see Figure 8)
See Figure 5
Guaranteed monotonic by design (see Figure 7)
All 0s loaded to DAC register (see Figure 18)
All 1s loaded to DAC register (see Figure 19)
Of FSR/°C
VDD ± 10%
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
RL = ∞
RL = 2 kΩ
VDD = 3 V
Coming out of power-down mode, VDD = 3 V
VREFIN = VDD = 3.6 V (per DAC channel)
TA = 25°C
LFCSP, TSSOP
WLCSP
All digital inputs
VDD = 3 V
VDD = 3 V
Rev. B | Page 5 of 32
Free Datasheet http://www.datasheet4u.com/

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AD5669R arduino
Data Sheet
AD5629R/AD5669R
Table 6. Pin Function Descriptions
Pin No.
LFCSP TSSOP WLCSP Mnemonic
15 1 B2 LDAC
16 2
13
24
35
46
57
68
A4 A0
B3 VDD
B4 VOUTA
B1 VOUTC
C4 VOUTE
C2 VOUTG
D3 VREFIN/VREFOUT
79
D2 CLR
8 10
9 11
10 12
11 13
12 14
13 15
C3
C1
D4
D1
A1
A3
VOUTH
VOUTF
VOUTD
VOUTB
GND
SDA
14 16
A4
SCL
17 N/A N/A Exposed Pad
(EPAD)
Description
Pulsing this pin low allows any or all DAC registers to be updated if the input registers
have new data. This allows all DAC outputs to simultaneously update. Alternatively,
this pin can be tied permanently low.
Address Input. Sets the least significant bit of the 7-bit slave address.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. Decouple the
supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
The AD5629R/AD5669R have a common pin for reference input and reference
output. When using the internal reference, this is the reference output pin. When
using an external reference, this is the reference input pin. The default for this pin is
as a reference input.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all
LDAC pulses are ignored. When CLR is activated, the input register and the DAC
register are updated with the data contained in the CLR code register—zero scale,
midscale, or full scale. The default setting clears the output to 0 V.
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Parts.
Serial Data Input. This is used in conjunction with the SCL line to clock data into or
out of the 32-bit input shift register. It is a bidirectional, open-drain data line that
should be pulled to the supply with an external pull-up resistor.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or
out of the 32-bit input shift register.
The exposed pad must be tied to GND.
Rev. B | Page 11 of 32
Free Datasheet http://www.datasheet4u.com/

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