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PDF 25L3206E Data sheet ( Hoja de datos )

Número de pieza 25L3206E
Descripción MX25L3206E
Fabricantes Macronix 
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1. 25L3206E






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MX25L3206E
MX25L3206E DATASHEET
P/N: PM1568
REV. 1.4, FEB. 23, 2012
1
Free Datasheet http://www.datasheet4u.com/

1 page




25L3206E pdf
MX25L3206E
FEATURES
32M-BIT [x 1 / x 2] CMOS SERIAL FLASH
GENERAL
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
33,554,432 x 1 bit structure or 16,777,216 x 2 bits (Dual Output mode) structure
• 1024 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 64 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Program Capability
- Byte base
- Page base (256 bytes)
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock
- Serial clock of Dual Output mode : 80MHz
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page
- Byte program time: 9us (typical)
- Fast erase time: 60ms(typ.) /sector ; 0.7s(typ.) /block
• Low Power Consumption
- Low active read current: 25mA(max.) at 86MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Standby current: 40uA (max.)
- Deep power-down mode 5uA (typical)
• Typical 100,000 erase/program cycles
• 20 years of data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP3~BP0 status bit defines the size of the area to be software protection against program and erase instruc-
tions
- Additional 512 bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1568
REV. 1.4, FEB. 23, 2012
5
Free Datasheet http://www.datasheet4u.com/

5 Page





25L3206E arduino
MX25L3206E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. The CS# falling time needs to
follow tCHCL spec.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge. The CS# rising time needs to follow tCLCH spec.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown in Figure 1.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, DREAD, RES, and
REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted
out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP, DP,
ENSO, EXSO, and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will
be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL CPHA
(Serial mode 0) 0
0 SCLK
(Serial mode 3) 1
1 SCLK
SI
SO
shift in
MSB
shift out
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1568
REV. 1.4, FEB. 23, 2012
11
Free Datasheet http://www.datasheet4u.com/

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