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Número de pieza | NAND512R4A2C | |
Descripción | NAND Flash Memories | |
Fabricantes | Numonyx | |
Logotipo | ||
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No Preview Available ! NAND512R3A2C NAND512R4A2C
NAND512W3A2C NAND512W4A2C
512 Mbit, 528 byte/264 word page,
1.8 V/3 V, NAND Flash memories
Features
● High density NAND Flash memories
– 512 Mbit memory array
– Cost effective solutions for mass
storage applications
● NAND interface
– x 8 or x 16 bus width
– Multiplexed Address/ Data
● Supply voltage: 1.8 V, 3.0 V
● Page size
– x 8 device: (512 + 16 spare) bytes
– x 16 device: (256 + 8 spare) words
● Block size
– x 8 device: (16 K + 512 spare) bytes
– x 16 device: (8 K + 256 spare) words
● Page Read/Program
– Random access:
12 µs (3 V)/15 µs (1.8 V) (max)
– Sequential access:
30 ns (3 V)/50 ns (1.8 V) (min)
– Page Program time: 200 µs (typ)
● Copy Back Program mode
● Fast Block Erase: 2 ms (typ)
● Status Register
● Electronic signature
● Chip Enable ‘don’t care’
● Serial Number option
Table 1.
Device summary
Reference
NAND512-A2C
1. x16 organization only available for MCP.
TSOP48 12 x 20 mm
FBGA
VFBGA55 8 x 10 x 1 mm
VFBGA63 9 x 11 x 1 mm
● Hardware Data Protection
– Program/Erase locked during Power
transitions
● Data integrity
– 100,000 Program/Erase cycles (with
ECC)
– 10 years Data Retention
● ECOPACK® packages
● Development tools
– Error Correction Code models
– Bad Blocks Management and Wear
Leveling algorithms
– Hardware simulation models
Part number
NAND512R3A2C
NAND512R4A2C(1)
NAND512W3A2C
NAND512W4A2C(1)
January 2008
Rev 2
1/51
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1
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1 page NAND512-A2C
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP48 connections - x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FBGA63 connections - x8 devices (top view through package) . . . . . . . . . . . . . . . . . . . . . 10
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pointer operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read (A,B,C) operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Page Program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Copy Back operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Bad Block management flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Equivalent testing circuit for AC characteristics measurement . . . . . . . . . . . . . . . . . . . . . . 35
Command Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Input Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Sequential Data Output after Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Read Status Register AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Read Electronic Signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Page Read A/ Read B operation AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Read C operation, One Page AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Page Program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Block Erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 46
Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 47
VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, package outline . . . . . . . . . . . . 48
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5 Page NAND512-A2C
2 Memory array organization
Memory array organization
The memory array is made up of NAND structures where 16 cells are connected in series.
The memory array is organized in blocks where each block contains 32 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store Error correction Codes, software
flags or Bad Block identification.
In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and
a spare area of 16 Bytes. In the x16 devices the pages are split into a 256 Word main area
and an 8 Word spare area. Refer to Figure 5: Memory array organization.
Bad blocks
The NAND Flash 528 Byte/ 264 Word Page devices may contain Bad Blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad
Blocks may develop during the lifetime of the device.
The Bad Block Information is written prior to shipping (refer to Section 7.1: Bad Block
management for more details).
Table 4 shows the minimum number of valid blocks in each device. The values shown
include both the Bad Blocks that are present when the device is shipped and the Bad Blocks
that could develop later on.
These blocks need to be managed using Bad Blocks Management, Block Replacement or
Error Correction Codes (refer to Section 7: Software algorithms).
Table 4. Valid blocks
Density of device
512 Mbits
Min
4016
Max
4096
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Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet NAND512R4A2C.PDF ] |
Número de pieza | Descripción | Fabricantes |
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