RK2818
Brief Technical Reference Manual
Support embedded DMA function
Tightly coprocessor in dsp system
Rev 1.0
z Graphics hardware accellerator (GPU)
3D feature
Four times and 16 times Full Scene Anti-Aliasing (FSAA).
Lines, squares, triangles and points.
Flat and Gouraud shading.
Perspective correct texturing.
Point sampling, bilinear, and trilinear filtering.
Programmable mipmap level-of-detail biasing.
Multitexturing, with three textures.
Dot3 bump mapping.
Alpha blending.
Stencil buffering.
Point sprites.
4-bit per texel texture compression, Ericsson Texture Compression
(ETC)
2D features
Lines, squares, triangles and points
ROP3/4
Arbitrary rotation and scaling
Alpha blending
Multitexture BitBLT
z External Memory Interface
Support SDRAM/Mobile SDRAM/DDRII/Mobile DDR separately
Support special SDRAM controller for high-performance video data transfer
Support Nor Flash/Nand Flash/SD/MMC/SDIO interface, Nor Flash interface is
only available when use SDRAM or Mobile SDRAM
Static/SDRAM Memory controller
Dynamic memory interface support , including SDR-SDRAM and Mobile
SDRAM
Asynchronous static memory device support including SRAM, ROM and
Nor Flash with or without asynchronous page mode
Support 2 chip selects for (Mobile) SDRAM and 2 chip selects for static
memory
Support 16bits or 32bits width data bus (Mobile) SDRAM and 8/16 bits
data bus static memory, it is programmable.
Support industrial standard (Mobile) SDRAM with a maximum of 256MB
of address space per chip select
4Mbytes access space per static memory support
Support (Mobile) SDRAM and Static Memory power-down mode
Support (Mobile) SDRAM self-refresh mode
Programmable arbitration priority for 6 slave data ports
DDRII/Mobile DDR Memory controller
Programmable select for DDRII or Mobile DDR function
Fully pipelined command, read and write data interface
Advanced bank look-ahead features for high memory throughput
Support one slave port for register set and 6 slave ports for data access
Separate asynchronous FIFOs for every slave ports to support different
frequency between AHB bus and DDR controller, and improve utility for
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6/4/2010