PDF FDMC86520DC Data sheet ( Hoja de datos )

Número de pieza	FDMC86520DC
Descripción	N-Channel Power Trench MOSFET
Fabricantes	Fairchild Semiconductor
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No Preview Available ! FDMC86520DC September 2012 N-Channel Dual CoolTM PowerTrench® MOSFET 60 V, 40 A, 6.3 mΩ Features General Description Dual CoolTM Top Side Cooling PQFN package Max rDS(on) = 6.3 mΩ at VGS = 10 V, ID = 17 A Max rDS(on) = 8.7 mΩ at VGS = 8 V, ID = 14.5 A High performance technology for extremely low rDS(on) RoHS Compliant This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process. Advancements in both silicon and Dual CoolTM package technologies have been combined to offer the lowest rDS(on) while maintaining excellent switching performance by extremely low Junction-to-Ambient thermal resistance. Applications Primary DC-DC Switch Motor Bridge Switch Synchronous Rectifier Pin 1 G S S S SD SD D D D D Top Power 33 Bottom MOSFET Maximum Ratings TA= 25 °C unless otherwise noted Symbol VDS VGS ID EAS PD TJ, TSTG Parameter Drain to Source Voltage Gate to Source Voltage Drain Current -Continuous -Continuous -Pulsed TC = 25 °C TA = 25 °C Single Pulse Avalanche Energy Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C Operating and Storage Junction Temperature Range Thermal Characteristics S G (Note 1a) (Note 3) (Note 1a) D D Ratings 60 ±20 40 17 80 128 73 3.0 -55 to + 150 Units V V A mJ W °C RθJC RθJC RθJA RθJA RθJA RθJA RθJA Thermal Resistance, Junction to Case Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Ambient Package Marking and Ordering Information Device Marking 86520 Device FDMC86520DC Package Dual CoolTM Power 33 (Top Source) (Bottom Drain) (Note 1a) (Note 1b) (Note 1i) (Note 1j) (Note 1k) 4.2 1.7 42 105 17 26 12 Reel Size 13’’ Tape Width 12 mm °C/W Quantity 3000 units ©2012 Fairchild Semiconductor Corporation FDMC86520DC Rev. C 1 www.fairchildsemi.com Free Datasheet http://www.datasheet4u.com/ 1 page Typical Characteristics TJ = 25 °C unless otherwise noted 10 ID = 17 A 8 6 VDD = 30 V VDD = 20 V VDD = 40 V 4 2 0 0 5 10 15 20 25 30 Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics 10000 1000 100 Ciss Coss 10 f = 1 MHz VGS = 0 V 1 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Crss 60 Figure8. CapacitancevsDrain to Source Voltage 100 TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 1 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) Figure9. Unclamped Inductive Switching Capability 100 90 VGS = 10 V 60 VGS = 8 V 30 Limited by Package RθJC = 1.7 oC/W 0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) Figure 10. Maximum Continuous Drain Current vs Case Temperature 150 100 300 SINGLE PULSE RθJA = 105 oC/W 10 100 TA = 25 oC 1 THIS AREA IS LIMITED BY rDS(on) 0.1 0.01 0.01 SINGLE PULSE TJ = MAX RATED RθJA = 105 oC/W TA = 25 oC 0.1 1 10 VDS, DRAIN to SOURCE VOLTAGE (V) 1 ms 10 ms 100 ms 1s 10 s DC 100 300 Figure 11. Forward Bias Safe Operating Area 10 1 10-3 10-2 10-1 1 10 t, PULSE WIDTH (sec) 100 Figure 12. Single Pulse Maximum Power Dissipation 1000 ©2012 Fairchild Semiconductor Corporation FDMC86520DC Rev. C 5 www.fairchildsemi.com Free Datasheet http://www.datasheet4u.com/ 5 Page

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