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PDF IDTCV144 Data sheet ( Hoja de datos )

Número de pieza IDTCV144
Descripción CLOCK
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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IDTCV144
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
IDTCV144
FEATURES:
• Power management control suitable for notebook applications
• One high precision PLL for CPU, SSC and N programming
• One high precision PLL for SRC/PCI, supports 100MHz output
frequency, SSC and N programming
• One high precision PLL for LVDS. Supports 100/96MHz output
frequency, SSC programming
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, index read/write
• Selectable output strength for REF
• Allows for CPU frequency to change to a slower frequency to
conserve power when an application is less execution-
intensive
• Smooth transition for N programming
• Available in TSSOP package
KEY SPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 250ps
• Static PLL frequency divide error for all clocks = 0ppm
DESCRIPTION:
IDTCV144 is a 56 pin clock device, incorporating both Intel CK410M and
CKSSCD requirements, for Intel advance P4 processors. The CPU output
bufferisdesignedtosupportupto400MHzprocessor. ThischiphasfourPLLs
inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This device
also implements Band-gap referenced IREF to reduce the impact of VDD variation
on differential outputs, which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, worse case 114
ppm,providinghighaccuracyoutputclock. EachCPU/SRC/LVDShasitsown
Spread Spectrum selection.
OUTPUTS:
• 2*0.7V current –mode differential CPU CLK pair
• 5*0.7V current –mode differential SRC CLK pair
• One CPU_ITP/SRC selectable CLK pair
• 6*PCI, 2 free running, 33.3MHz
• 1*96MHz, 1*48MHz
• 2*REF
• One 100/96 MHz differential LVDS
FUNCTIONAL BLOCK DIAGRAM
X1
X2
SDATA
SCLK
XTAL
Osc Amp
SM Bus
Controller
PLL1
SSC
N Programmable
PLL2
SSC
VTT_PWRGD#/PD
SEL100/96#
CLKREQA#
CLKREQB#
FSA.B.C
PCI_STOP#
CPU_STOP#
SEL
100/96MHz
Control
Logic
PLL3
SSC
N Programmable
PLL4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
1
CPU CLK
Output Buffer
Stop Logic
IREF
LVDS CLK
Output Buffer
Stop Logic
IREF
SRC CLK
Output Buffer
Stop Logic
IREF
48MHz/96MHz
Output BUffer
ITP_EN
CPU[1:0]
CPU_ITP/SRC7
REF
LVDS
SRC[5:1]
PCI[3:0], PCIF[1:0]
48MHz
DOT96
DECEMBER 2004
DSC 6597/3
Free Datasheet http://www.datasheet4u.com/

1 page




IDTCV144 pdf
IDTCV144
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
SSC MAGNITUDE CONTROL FOR CPU,
SRC, AND SMC
SMC[2:0]
000 -0.25
001 -0.5
010 -0.75
011 -1
100 ±0.125
101 ±0.25
110 ±0.375
111 ±0.5
RESOLUTION
CPU (MHz)
100
133
166
200
266
333
400
COMMERCIALTEMPERATURERANGE
Resolution
0.666667
0.666667
1.333333
1.333333
1.333333
2.666667
2.666667
N=
150
200
125
150
200
125
150
SEL 100/96# CONFIGURATION
SEL 100/96#
LVDS Frequency
Unit
0 96 MHz
1 100 MHz
S.E. CLOCK STRENGTH SELECTION
(PCI, REF, USB48)
Str[1:0]
Level
00 1
01 0.8
10 0.6
11 1.2
SPREAD SPECTRUM CONTROL
SELECTION FOR LVDS
S[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Spread
-0.8%
-1%
-1.25%
-1.5%
-1.75%
-2%
-0.3%
-0.5%
±0.3%
±0.4%
±0.5%
±0.6%
±0.8%
±1%
±1.25%
±1.5%
5
Free Datasheet http://www.datasheet4u.com/

5 Page





IDTCV144 arduino
IDTCV144
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
VIH
VIL
VIH_FS
VIL_FS
IIH
IIL1
IIL2
IDD3.3OP
IDD3.3PD
Parameter
Input HIGH Voltage
Input LOW Voltage
LOW Voltage, HIGH Threshold
LOW Voltage, LOW Threshold
Input HIGH Current
Input LOW Current
Input LOW Current
Operating Supply Current
Powerdown Current
FI
LPIN
CIN
COUT
CINX
COUTX
TSTAB
Input Frequency(1)
Pin Inductance(2)
Input Capacitance(2)
Clock Stabilization(2,3)
Modulation Frequency(2)
TDRIVE_SRC(2)
TDRIVE_PD(2)
TFALL_PD(2)
TRISE_PD(3)
TDRIVE_CPU_STOP#(2)
TFALL_CPU_STOP#(2)
TRISE_CPU_STOP#(3)
Test Conditions
3.3V ± 5%
3.3V ± 5%
For FSA.B.C test_mode
For FSA.B.C test_mode
VIN = VDD
VIN = 0V, inputs with no pull-up resistors
VIN = 0V, inputs with pull-up resistors
Full active, CL = full load
All differential pairs driven
All differential pairs tri-stated
VDD = 3.3V
Logic inputs
Output pin capacitance
XTAL_IN
XTAL_OUT
From VDD power-up or de-assertion of PD to first clock
Triangular modulation
SRC output enable after PCI_STOP# de-assertion
CPU output enable after PD de-assertion
Fall time of PD
Rise time of PD
CPU output enable after CPU_STOP# de-assertion
Fall time of CPU_STOP#
Rise time of CPU_STOP#
Min.
2
VSS - 0.3
0.7
VSS - 0.3
–5
–5
–200
30
Typ.
14.31818
Max.
VDD + 0.3
0.8
VDD + 0.3
0.35
5
400
70
12
7
5
6
5
12
1.8
33
15
300
5
5
10
5
5
Unit
V
V
V
V
µA
µA
µA
mA
mA
MHz
nH
pF
ms
KHz
ns
us
ns
ns
us
ns
ns
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
11
Free Datasheet http://www.datasheet4u.com/

11 Page







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