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Número de pieza K7A803609A
Descripción 256Kx36 & 512Kx18 Synchronous SRAM
Fabricantes Samsung semiconductor 
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K7A803609A
K7A801809A
256Kx36 & 512Kx18 Synchronous SRAM
Document Title
256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
0.0
1.0
History
Initial draft
1. Final spec Release.
Draft Date Remark
May. 24 . 2000 Preliminary
July. 03. 2000 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
July 2000
Rev 1.0
Free Datasheet http://www.datasheet4u.com/

1 page




K7A803609A pdf
K7A803609A
K7A801809A
256Kx36 & 512Kx18 Synchronous SRAM
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7A803609A(256Kx36)
123456
A VDDQ A
A ADSP A
A
B NC CS2 A ADSC A
A
C NC A
A VDD A
A
D
DQc
DQPc
VSS
NC
VSS DQPb
E
DQc
DQc
VSS
CS1
VSS
DQb
F
VDDQ
DQc
VSS
OE
VSS DQb
G
DQc
DQc
WEc
ADV
WEb
DQb
H
DQc
DQc
VSS
GW
VSS DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
K
DQd
DQd
VSS
CLK
VSS
DQa
L
DQd
DQd
WEd
NC
WEa
DQa
M
VDDQ
DQd
VSS
BW
VSS DQa
N
DQd
DQd
VSS
A1*
VSS DQa
P
DQd
DQPd
VSS
A0*
VSS DQPa
R
NC
A
LBO
VDD
NC
A
T NC NC A A A NC
U
VDDQ
NC
NC
NC
NC
NC
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
7
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
ZZ
VDDQ
PIN NAME
SYMBOL
A
A0,A1
ADV
ADSP
ADSC
CLK
CS1
CS2
WEx
(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
PIN NAME
Address Inputs
Burst Count Address
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
SYMBOL
VDD
VSS
N.C.
DQa
DQb
DQc
DQd
DQPa~Pd
VDDQ
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
Output Power Supply
(2.5V or 3.3V)
- 5 - July 2000
Rev 1.0

5 Page





K7A803609A arduino
K7A803609A
K7A801809A
Output Load(A)
Dout
Zo=50
256Kx36 & 512Kx18 Synchronous SRAM
RL=50
30pF*
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
Dout
319Ω / 1667
353Ω / 1538
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
PARAMETER
Symbol
-22
Min Max
-20
MIN MAX
-18
Min Max
UNIT
Cycle Time
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
tCYC
tCD
tOE
tLZC
tOH
tLZOE
tHZOE
tHZC
4.4 - 5.0 - 5.4 - ns
- 2.8 - 3.1 - 3.3 ns
- 2.8 - 3.1 - 3.3 ns
0 - 0 - 0 - ns
1.0 - 1.0 - 1.0 - ns
0 - 0 - 0 - ns
- 2.8 - 3.0 - 3.0 ns
1.0 2.8 1.0 3.0 1.0 3.0 ns
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
tCH 1.8 - 2.0 - 2.4 - ns
tCL 1.8 - 2.0 - 2.4 - ns
tAS 1.4 - 1.4 - 1.4 - ns
Address Status Setup to Clock High
tSS 1.4 - 1.4 - 1.4 - ns
Data Setup to Clock High
tDS 1.4 - 1.4 - 1.4 - ns
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
tWS 1.4 - 1.4 - 1.4 - ns
tADVS 1.4 - 1.4 - 1.4 - ns
tCSS 1.4 - 1.4 - 1.4 - ns
tAH 0.4 - 0.4 - 0.4 - ns
tSH 0.4 - 0.4 - 0.4 - ns
tDH 0.4 - 0.4 - 0.4 - ns
tWH 0.4 - 0.4 - 0.4 - ns
tADVH 0.4 - 0.4 - 0.4 - ns
tCSH
0.4 - 0.4 - 0.4 - ns
ZZ High to Power Down
ZZ Low to Power Up
tPDS 2 - 2 - 2 - cycle
tPUS 2 - 2 - 2 - cycle
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
- 11 -
July 2000
Rev 1.0

11 Page







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