DataSheet.es    


PDF FAH4830 Data sheet ( Hoja de datos )

Número de pieza FAH4830
Descripción Haptic Driver
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de FAH4830 (archivo pdf) en la parte inferior de esta página.


Total 15 Páginas

No Preview Available ! FAH4830 Hoja de datos, Descripción, Manual

January 2013
FAH4830
Haptic Driver for DC Motors (ERMs) and Linear
Resonant Actuators (LRAs)
Features
Direct Drive of ERM and LRA Motors
External PWM Input (10 kHz to 50 kHz)
External Motor Enable/Disable Input
Internal Mode-Select Register: ERM or LRA
Low Standby Current: <500 nA
Fast Wake-up Time
Nearly Rail-to-Rail Output Swing
Register-Based Control by I2C
Over Driving Motor Control
Under-Voltage, Over-Current, and Over-
Temperature Protections
Settable Filter and External Gain Control
Package: 10-Lead MLP
Applications
Mobile Phones
Handheld Devices
Any Key-Pad Interface
Related Resources
AN-5067 — PCB Land Pattern Design and Surface-
Mount Guidelines for MLP Packages
Description
The FAH4830 is a high-performance enhanced haptic
drive for mobile phone and other hand-held devices.
The haptic driver takes a single-ended PWM input
signal to control a DC motor. It can drive both Eccentric
Rotating Mass (ERM) and Linear Resonant Actuator
(LRA) motors. The device utilizes an external 10 kHz to
50 kHz PWM signal capable of meeting the wide range
of resonant frequencies.
The FAH4830 has its own register maps accessible via
I2C serial communication. A gain control setting can be
used to help prevent PWM noise from getting into the
motor and to control the maximum output voltage on the
motor. For ERM motors, the over-drive control block is
designed to control the inertial momentum of the motor.
Figure 1. Block Diagram
Ordering Information
Part Number Operating Temperature Range
FAH4830MPX
-40°C to +85°C
Package
10-Lead, Dual, JEDEC MO-229,
3mm Square, Molded Leadless
Package (MLP)
Packing Method
3000 Units on
Tape & Reel
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
www.fairchildsemi.com

1 page




FAH4830 pdf
I2C DC Electrical Characteristics
TA = 25°C, VDD = 3.3 V, and VLDO = 3.0 V unless otherwise noted.
Symbol
Parameter
VIL Low-Level Input Voltage
VIH High-Level Input Voltage
VOL
Low-Level Output Voltage at 3 mA Sink Current
(Open-Drain or Open-Collector)
IIH High-Level Input Current of Each I/O Pin, Input Voltage = VDD
IIL Low-Level Input Current of Each I/O Pin, Input Voltage = 0 V
Fast Mode (400kHz)
Min.
Max.
Unit
-0.3 0.6
V
1.3 V
0 0.4 V
-1 1 µA
-1 1 µA
I2C AC Electrical Characteristics
Symbol
Parameter
Fast Mode (400kHz)
Min.
Max.
Unit
fSCL SCL Clock Frequency
0 400 kHz
tHD;STA Hold Time (Repeated) START Condition
0.6 µs
tLOW Low Period of SCL Clock
1.3 µs
tHIGH High Period of SCL Clock
0.6 µs
tSU;STA Set-up Time for Repeated START Condition
0.6 µs
tHD;DAT
tSU;DAT
tr
tf
Data Hold Time
Data Set-up Time(2)
Rise Time of SDA and SCL Signals(3)
Fall Time of SDA and SCL Signals(3)
0
100
20+0.1Cb
20+0.1Cb
0.9
300
300
µs
ns
ns
ns
tSU;STO Set-up Time for STOP Condition
0.6 µs
tBUF Bus-Free Time between STOP and START Conditions 1.3 µs
tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns
Notes:
2. A Fast-Mode I2C Bus® device can be used in a Standard-Mode I2C bus system, but the requirement tSU;DAT
250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
Serial Data (SDA) line tr_max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C Bus
specification) before the SCL line is released.
3. Cb equals the total capacitance of one bus line in pf. If mixed with High-Speed Mode devices, faster fall times are
allowed according to the I2C specification.
Figure 4. Definition of Timing for Full-Speed Mode Devices on the I2C Bus
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
5
www.fairchildsemi.com

5 Page





FAH4830 arduino
Figure 11. ERM System Block Diagram
Table 7. ERM Motor Function
PWM Duty Cycle
VDD
90/10%
PWM
Duty
Cycle
GND
VDD
50/50%
PWM
Duty
Cycle
GND
ERM Drive Voltage
10/90%
PWM
Duty
Cycle
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
11
www.fairchildsemi.com

11 Page







PáginasTotal 15 Páginas
PDF Descargar[ Datasheet FAH4830.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
FAH4830Haptic DriverFairchild Semiconductor
Fairchild Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar