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Número de pieza | EP82562ET | |
Descripción | 10/100 Mbps Platform LAN Connect | |
Fabricantes | Intel | |
Logotipo | ||
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No Preview Available ! 82562ET 10/100 Mbps Platform LAN
Connect (PLC)
Networking Silicon
Datasheet
Product Features
■ IEEE 802.3 10BASE-T/100BASE-TX
compliant physical layer interface
■ IEEE 802.3u Auto-Negotiation support
■ Digital Adaptive Equalization control
■ Link status interrupt capability
■ XOR tree mode support
■ 3-port LED support (speed, link and
activity)
■ 10BASE-T auto-polarity correction
■ LAN Connect Interface
■ Diagnostic loopback mode
■ 1:1 transmit transformer ratio support
■ Low power (less than 300 mW in active
transmit mode)
■ Reduced power in “unplugged mode” (less
than 50 mW)
■ Automatic detection of “unplugged mode”
■ 3.3 V device
■ 48-pin Shrink Small Outline Package
Revision 1.4
November 2006
Free Datasheet http://www.datasheet4u.com/
1 page 1.0
1.1
1.2
1.3
Networking Silicon — 82562ET
Introduction
Overview
The Intel® 82562ET is a highly-integrated Platform LAN Connect device designed for 10 or 100
Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards. The
IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5
unshielded twisted pair cable or Type 1 shielded twisted pair cable.
The 82562ET complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full
Duplex Flow Control standard. The 82563ET also includes a PHY interface compliant to the
current platform LAN connect interface.
Features
• IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface
• IEEE 802.3u Auto-Negotiation support
• Digital Adaptive Equalization control
• Link status interrupt capability
• XOR Tree mode support for board testing
• 3-port LED support (speed, link and activity)
• 10BASE-T auto-polarity correction
• Diagnostic loopback mode
• 1:1 transmit transformer ratio support
• Low power (less than 300 mW in active transmit mode)
• Reduced power in “unplugged mode” (less than 50 mW)
• Automatic detection of “unplugged mode”
• 3.3 V device
• 48-pin Shrink Small Outline Package
• Platform LAN connect interface support
References
• IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and
Electronics Engineers
• 82555 10/100 Mbps LAN Physical Layer Interface Datasheet, Intel Corporation
• LAN Connect Interface Specification, Intel Corporation
Datasheet
1
5 Page 3.6
3.7
Networking Silicon — 82562ET
LED Pins
Pin Name
LILED#
ACTLED#
SPDLED#
Pin
Number
Type
27 O
32 O
31 O
Description
Link Integrity LED. The LED is active low and the Link Integrity LED pin
indicates link status in either 10BASE-T or 100BASE-TX mode. If a link is
present in either mode, the LILED is asserted.
Activity LED. The LED is active low and the Activity LED signal indicates
either receive or transmit activity. When no activity is present, the LED is
off. The Activity LED will flicker when activity is present. The flicker rate
depends on the activity load.
The individual address LED control bit (Word A hexadecimal, bit 4) in the
ICH2 EEPROM can select the ACTLED# behavior. It controls the Activity
LED (ACTLED) functionality in Wake on LAN (WOL) mode.
0 = In WOL mode, the ACTLED is activated by the transmission and
reception of broadcast and individual address match packets.
1 = In WOL mode, the ACTLED is activated by the transmission and
reception of individual address match packets only.
This bit is configured by the OEM and is activated by a transmission and
reception of individual address match packets.
Speed LED. The LED is active low and the Speed LED signal indicates
the speed of operation, either 10 Mbps or 100 Mbps. The Speed LED is
on during 100BASE-TX operation and off in 10BASE-T mode.
Miscellaneous Control Pins
Pin Name
ADV10
ISOL_TCK
ISOL_TI
Pin
Number
Type
41 I
30 I
28 I
Description
Advertise 10 Mbps Only. The Advertise 10 Mbps Only signal is asserted
high, and the 82562ET advertises only 10BASE-T technology during
Auto-Negotiation processes in this state. Otherwise, the 82562ET
advertises all of its technologies.
Note: ADV10 has an internal pull-down resistor.
Test Clock. The Test Clock signal sets the device into asynchronous test
mode in conjunction with the Test Input, Test Execute and Test Enable
pins (refer to Table 1, “82562ET Hardware Configuration” on page 3).
In the manufacturing test mode, it acts as the test clock.
Note: ISOL_TCK has an internal pull-down resistor.
Test Input. The Test Input signal sets the device into asynchronous test
mode in conjunction with the Test Clock, Test Execute and Test Enable
pins (refer to Table 1, “82562ET Hardware Configuration” on page 3).
In the manufacturing test mode, it acts as the test data input pin.
Note: ISOL_TI has an internal pull-down resistor.
Datasheet
7
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet EP82562ET.PDF ] |
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