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PDF IDT9173B Data sheet ( Hoja de datos )

Número de pieza IDT9173B
Descripción VIDEO GENLOCK PLL
Fabricantes IDT 
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VIDEO GENLOCK PLL
PRELIMINARY DATASHEET
IDT9173B
Description
The IDT9173B provide the analog PLL circuit blocks to
implement a frequency multiplier. Because the device is
configured to use an external divider in the PLL clock
feedback path, a large divider can be used to result in a
large frequency multiplication ratio. This is useful when
using a low frequency input clock to generate a high
frequency output clock. The IDT9173B contains a phase
detector, charge pump, loop filter, and voltage-controlled
oscillator (VCO). The ICS674-01 can be used as the
external feedback divider.
A common application of the IDT9173B is the
implementation of a video genlock circuit. Because of this,
the IDT9173B inputs operate on the negative-going clock
edge.
The IDT9173B is pin and function compatible to the
AV9173-01/15.
Features
Phase-detector/VCO circuit block
Ideal for genlock system
Reference clock range 12 kHz to 1 MHz for full output
clock range
Output clock range of 1.25 to 75 MHz (-01), and 0.625 to
37.5 MHz (-15). See “Allowable Input Frequency to
Output Frequency” table for conditions
On-chip loop filter
Single 5 V power supply
Low power CMOS technology
8-pin SOIC package
Block Diagram
http://www.DataSheet4U.net/
IDT™ VIDEO GENLOCK PLL
1
IDT9173B
REV A 092308
datasheet pdf - http://www.DataSheet4U.net/

1 page




IDT9173B pdf
IDT9173B
VIDEO GENLOCK PLL
CLOCK SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise, VDD = 5 V ±5%, Ambient Temperature 0 to +70° C
Parameter
Symbol Conditions
Min.
Operating Supply Current
IDD No load,50 MHz
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage 1
Output High Voltage 1
Output High Voltage 1
VIH
VIL
IIL
IIH
VOL
VOH1
VOH2
VOH3
VDD = 5 V
VDD = 5 V
VIN = 0V
VIN = VDD
IOL = 8 mA
IOH = -1 mA
IOH = -4 mA
IOH = -8 mA
2.0
-5
-5
VDD-0.4
VDD-0.8
2.4
Typ.
20
Max.
50
0.8
5
0.4
Units
mA
V
V
µA
µA
V
V
V
V
Notes:
1. Duty cycle measured at 1.4 V.
2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical
pixels.
3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4.
AC Electrical Characteristics
Unless stated otherwise, VDD = 5 V ±5%, Ambient Temperature 0 to +70° C
http://www.DataSheet4U.net/
Parameter
Symbol
Conditions
Output Clock Rise Time 1
Output Clock Fall Time 1
Output Rise Time 1
Output Rise Time 1
Output Fall Time 1
Output Fall Time 1
Output Duty Cycle 1
ICLKr
ICLKf
tr1
tr2
tf1
tf2
15 pF load, 20% to 80%
15 pF load, 20% to 80%
15 pF load, 80% to 20%
15 pF load, 80% to 20%
15 pF load
One-Sigma Jitter 1, 5
Jitter, Absolute 1, 5
One-Sigma Jitter 1, 5
Jitter, Absolute 1, 5
Line-to-Line Jitter 1, Absolute 2
Input Frequency 1, IN or FBIN
T1S1
TABS1
T1S2
TABS2
TLABS
fIN
CLK1 frequency 3, 25 MHz
CLK1 frequency 3, 25 MHz
CLK1 frequency < 25 MHz
CLK1 frequency < 25 MHz
see allowable fi below
Min.
40
-400
12
Typ.
0.6
1.4
0.8
0.8
47
120
±250
±4
Max.
10
10
1.5
3.0
2.0
2.0
55
250
400
1
2
1000
Units
ns
ns
ns
ns
ns
ns
%
ps
ps
%
%
ns
kHz
IDT™ VIDEO GENLOCK PLL
5
IDT9173B
REV A 092308
datasheet pdf - http://www.DataSheet4U.net/

5 Page










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