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PDF TCP-3068H Data sheet ( Hoja de datos )

Número de pieza TCP-3068H
Descripción Passive Tunable Integrated Circuits
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TCP-3068H
Advance Information
6.8 pF Passive Tunable
Integrated Circuits (PTIC)
Introduction
ON Semiconductor’s PTICs have excellent RF performance and
power consumption, making them suitable for any mobile handset or
radio application. The fundamental building block of our PTIC
product line is a tunable material called ParaScant, based on Barium
Strontium Titanate (BST). PTICs have the ability to change their
capacitance from a supplied bias voltage generated by the Control IC.
The 6.8 pF PTICs are available as wafer-level chip scale packages
(WLCSP) and in QFN packages for easy mounting directly on printed
circuit boards.
Key Features
High Tuning Range and Operation up to 20 V
Usable Frequency Range: from 700 MHz to 2.7 GHz
High Quality Factor (Q) for Low Loss
High Power Handling Capability
Compatible with PTIC Control IC TCC-103
WLCSP Package: 0.722 x 1.179 x 0.611 mm (12 pillar)
QFN Package: 1.200 x 1.600 x 0.950 mm
QFN: MSL2 Moisture Sensitivity Level (per JSTD020) http://www.DataSheet4U.net/
PbFree and RoHS Compliant
Typical Applications
Multi-band, Multi-standard, Advanced and Simple Mobile Phones
Tunable Antenna Matching Networks
Tunable RF Filters
Active Antennas
http://onsemi.com
WLCSP
12 pillar
CASE TBD
QFN
6 pin
CASE TBD
QFN MARKING DIAGRAM
X.XH
X.X = 6.8
H = High Tuning
FUNCTIONAL BLOCK DIAGRAM
PTIC
RF1 RF2
Bias
Figure 1. PTIC Functional Block Diagram
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2013
May, 2013 Rev. P1
1
ORDERING INFORMATION
Device
Package
Shipping
TCP3068HDT WLCSP
(PbFree)
4000 Units /
7” Reel
TCP3068HQT
QFN
(PbFree)
8000 Units /
13” Reel
For detailed ordering information, including part
number definition and capacitance (pF) see the
package dimensions section on page 7 of this
datasheet.
Publication Order Number:
TCP3068H/D
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TCP-3068H pdf
TCP3068H
Wafer Level Chip Scale Package (WLCSP) Layout and Dimensional Information
A2
A1
D3
D2
(Copper Pillar
Height)
D1
C1 C2
C3 N/C Bias
B3
RF1 RF2
RF1 RF2
B2
RF1 RF2
RF1 RF2
B2
RF1 RF2
2X 0.104 mm (Typ)
(Copper Pillar)
2X 0.069 mm (Typ)
(Copper Pillar)
RF Pillars
0.104 mm (Typ)
Top View
(Pillars Down)
Note:
2X means 2 sites with the specific value
3X means 3 sites with the specific value
4X means 4 sites with the specific value
Side View
B4 B1
Bottom View
(Pillars Up)
Figure 7. WLCSP Pin Markers and Dimensions
RF Pillars
0.069 mm (Typ)
Table 3. PACKAGE DIMENSIONS
(All dimensions are in milimeters)
WLCSP * DIM Nominal Max
8P A1 0.879
10P A1 1.029
12P A1 1.179
14P A1 1.329
ALL A2 0.722
ALL B1 0.460
ALL B2 0.150
ALL B3 0.300
ALL B4 0.130
ALL C1 0.148
ALL C2 0.425
ALL C3 0.130
ALL D1 0.530
ALL D2 0.081
*Total number of pillars
Device
1.2, 2.7 pF
3.3, 3.9 pF
4.7, 5.6, 6.8, 8.2 pF
http://www.DataSheet4U.net/
Note:
0.9 mm pad layout is standard for all products. Shorter pad
layouts can be considered for smaller products.
Figure 8. Recommended Pad Layout
http://onsemi.com
5
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