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Número de pieza | 2N7002LT1 | |
Descripción | CASE 318-08/ STYLE 21 SOT-23 (TO-236AB) | |
Fabricantes | Motorola Inc | |
Logotipo | ||
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No Preview Available ! MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by 2N7002LT1/D
TMOS FET Transistor
N–Channel Enhancement
3 DRAIN
2N7002LT1
Motorola Preferred Device
1
GATE
2 SOURCE
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Drain Current — Continuous TC = 25°C(1)
Drain Current — Continuous TC = 100°C(1)
Drain Current — Pulsed(2)
VDSS
VDGR
ID
ID
IDM
Gate–Source Voltage
— Continuous
— Non–repetitive (tp ≤ 50 µs)
VGS
VGSM
THERMAL CHARACTERISTICS
Characteristic
Total Device Dissipation FR–5 Board,(3) TA = 25°C
Derate above 25°C
60
60
± 115
± 75
± 800
± 20
± 40
Vdc
Vdc
mAdc
Vdc
Vpk
Symbol
PD
Thermal Resistance, Junction to Ambient
Total Device Dissipation
Alumina Substrate,(4) TA = 25°C
Derate above 25°C
RθJA
PD
Thermal Resistance, Junction to Ambient
Junction and Storage Temperature
DEVICE MARKING
RθJA
TJ, Tstg
2N7002LT1 = 702
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0, ID = 10 µAdc)
V(BR)DSS
Zero Gate Voltage Drain Current
(VGS = 0, VDS = 60 Vdc)
TJ = 25°C
TJ = 125°C
IDSS
Gate–Body Leakage Current, Forward
(VGS = 20 Vdc)
IGSSF
Gate–Body Leakage Current, Reverse
(VGS = – 20 Vdc)
IGSSR
1. The Power Dissipation of the package may result in a lower continuous drain current.
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
3. FR–5 = 1.0 x 0.75 x 0.062 in.
4. Alumina = 0.4 x 0.3 x 0.025 in 99.5% alumina.
3
1
2
CASE 318 – 08, STYLE 21
SOT– 23 (TO – 236AB)
Max
225
1.8
556
300
2.4
417
– 55 to +150
Unit
mW
mW/°C
°C/W
mW
mW/°C
°C/W
°C
Min Typ Max Unit
60 — — Vdc
— — 1.0 µAdc
— — 500
— — 100 nAdc
—
—
–100
nAdc
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
© Motorola, Inc. 1997
1
1 page PACKAGE DIMENSIONS
2N7002LT1
A
L
3
BS
12
VG
C
DH
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIUMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
KJ
INCHES
DIM MIN MAX
A 0.1102 0.1197
B 0.0472 0.0551
C 0.0350 0.0440
D 0.0150 0.0200
G 0.0701 0.0807
H 0.0005 0.0040
J 0.0034 0.0070
K 0.0140 0.0285
L 0.0350 0.0401
S 0.0830 0.1039
V 0.0177 0.0236
MILLIMETERS
MIN MAX
2.80 3.04
1.20 1.40
0.89 1.11
0.37 0.50
1.78 2.04
0.013 0.100
0.085 0.177
0.35 0.69
0.89 1.02
2.10 2.64
0.45 0.60
CASE 318–08
ISSUE AF
SOT–23 (TO–236AB)
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
Motorola Small–Signal Transistors, FETs and Diodes Device Data
5
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet 2N7002LT1.PDF ] |
Número de pieza | Descripción | Fabricantes |
2N7002LT1 | CASE 318-08/ STYLE 21 SOT-23 (TO-236AB) | Motorola Inc |
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