PDF DAC1627D1G25 Data sheet ( Hoja de datos )

Número de pieza	DAC1627D1G25
Descripción	Dual 16-bit DAC
Fabricantes	NXP Semiconductors
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No Preview Available ! DAC1627D1G25 Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating Rev. 1 — 29 April 2011 Objective data sheet 1. General description The DAC1627D1G25 is a high-speed 16-bit dual channel Digital-to-Analog Converter (DAC) with selectable ×2, ×4 and ×8 interpolating filters optimized for multi-carrier and broadband wireless transmitters at sample rates of up to 1.25 Gsps. Supplied from a 3.3 V and a 1.8 V source, the DAC1627D1G25 integrates a differential scalable output current up to 31.8 mA. The DAC1627D1G25 is capable of meeting multi-carrier GSM specifications. For example, with an output frequency of 150 MHz and a DAC clock frequency of 1.22 Gsps the full-scale dynamic range is: • SFDRRBW = 85 dBc (bandwidth = 250 MHz) • IMD3 = 85 dBc The Serial Peripheral Interface (SPI) provides full control of the DAC1627D1G25. The DAC1627D1G25 integrates a Low Voltage Differential Signaling (LVDS) Double Data Rate (DDR) receiver interface, with an on-chip 100 Ω termination. The LVDS DDR interface accepts a multiplex input data stream such as interleaved or folded. An internal LVDS input auto-calibration ensures the robustness and stability of the interface. http://www.DataSheet4U.net/ Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. The mixer frequency is set by a 40-bit Numerically Controlled Oscillator (NCO). High resolution internal gain, phase and offset control provide outstanding image and Local Oscillator (LO) signal rejection at the system analog modulator output. An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at the DAC output. Multiple device synchronization allows synchronization of the outputs of multiple DAC devices. MDS guarantees a maximum skew of one output clock period between several devices. The DAC1627D1G25 includes a very low noise capacitor-free integrated Phase-Locked Loop (PLL) multiplier which generates a DAC clock rate from the LVDS clock rate. The DAC1627D1G25 is available in a HVQFN72 package (10 mm × 10 mm). datasheet pdf - http://www.DataSheet4U.net/ 1 page NXP Semiconductors DAC1627D1G25 Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating DAC1627D1G25 Objective data sheet Table 2. Pin description …continued Symbol Pin Type[1] Description LD[14]P 10 I LVDS positive input bit 14[2] LD[14]N 11 I LVDS negative input bit 14[2] VDDD(1V8) LD[13]P 12 P 13 I 1.8 V digital power supply LVDS positive input bit 13[2] LD[13]N 14 I LVDS negative input bit 13[2] LD[12]P 15 I LVDS positive input bit 12[2] LD[12]N 16 I LVDS negative input bit 12[2] LD[11]P 17 I LVDS positive input bit 11[2] LD[11]N 18 I LVDS negative input bit 11[2] VDDD(1V8) LD[10]P 19 P 20 I 1.8 V digital power supply LVDS positive input bit 10[2] LD[10]N 21 I LVDS negative input bit 10[2] LD[9]P 22 I LVDS positive input bit 9[2] LD[9]N 23 I LVDS negative input bit 9[2] LD[8]P 24 I LVDS positive input bit 8[2] LD[8]N 25 I LVDS negative input bit 8[2] VDDD(1V8) LCKP 26 P 27 I 1.8 V digital power supply LVDS positive data clock input LCKN 28 I LVDS negative data clock input GND_DP 29 G connect to groundhttp://www.DataSheet4U.net/ LD[7]P 30 I LVDS positive input bit 7[2] LD[7]N 31 I LVDS negative input bit 7[2] LD[6]P 32 I LVDS positive input bit 6[2] LD[6]N 33 I LVDS negative input bit 6[2] LD[5]P 34 I LVDS positive input bit 5[2] LD[5]N 35 I LVDS negative input bit 5[2] VDDD(1V8) LD[4]P 36 P 37 I 1.8 V digital power supply LVDS positive input bit 4[2] LD[4]N 38 I LVDS negative input bit 4[2] LD[3]P 39 I LVDS positive input bit 3[2] LD[3]N 40 I LVDS negative input bit 3[2] LD[2]P 41 I LVDS positive input bit 2[2] LD[2]N 42 I LVDS negative input bit 2[2] VDDD(1V8) LD[1]P 43 P 44 I 1.8 V digital power supply LVDS positive input bit 1[2] LD[1]N 45 I LVDS negative input bit 1[2] LD[0]P 46 I LVDS positive input bit 0[2] LD[0]N 47 I LVDS negative input bit 0[2] IO1 48 IO IO port bit 1 IO0 49 IO IO port bit 0 SDO 50 O SPI data output All information provided in this document is subject to legal disclaimers. Rev. 1 — 29 April 2011 © NXP B.V. 2011. All rights reserved. 5 of 69 datasheet pdf - http://www.DataSheet4U.net/ 5 Page NXP Semiconductors DAC1627D1G25 Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 5. Characteristics …continued VDDA(1V8) = 1.8 V; VDDD(1V8) = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition defined in Figure 22; output level = 1 V (p-p). Symbol Parameter Conditions Test [1] Min Typ Max Unit Low power NCO frequency range; fs = 1000 MHz fNCO NCO frequency two’s complement coding reg value = F8000000000h D reg value = F8000000000h D reg value = 00000000000h D reg value = 08000000000h D reg value = 7FFFFFFFFFh D fstep step frequency Dynamic performance D SFDR SFDRRBW spurious-free dynamic range restricted bandwidth spurious-free dynamic range fdata = 307.2 MHz; fs = 1228.8 Msps; BW = fs / 2 fo = 20 MHz at −1 dBFS; I fdata = 245.76 MHz; fs = 983.04 Msps; BW = fs / 2 fo = 20 MHz at −1 dBFS I fdata = 245.76 MHz; fs = 983.04 Msps; fo = 150 MHz http://www.DataSheet4U.net/ BW = 100 MHz I BW = 180 MHz I fdata = 307.2 MHz; fs = 1228.8 Msps; fo = 210 MHz BW = 100 MHz I BW = 180 MHz I IMD3 third-order intermodulation distortion fdata = 245.76 MHz; fs = 983.04 Msps; fo1 = 20 MHz; fo2 = 21 MHz; ×4 interpolation; output level = −1 dBFS I fdata = 245.76 MHz; fs = 983.04 Msps; fo1 = 152 MHz; fo2 = 155.1 MHz; fs = 1228.8 MHz; ×4 interpolation; output level = −1 dBFS I - - - - - - - - - - - - - - −500 −31.25 0 +31.25 +468.75 31.25 - - - - - - 83 - 85 - 90 <tbd> - - <tbd> <tbd> 93 - - - 85 - MHz MHz Hz MHz MHz MHz dBc dBc dBc dBc dBc dBc dBc dBc DAC1627D1G25 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 29 April 2011 © NXP B.V. 2011. All rights reserved. 11 of 69 datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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