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PDF MAX14920 Data sheet ( Hoja de datos )

Número de pieza MAX14920
Descripción (MAX14920 / MAX14921) High-Accuracy 12-/16-Cell Measurement AFEs
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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No Preview Available ! MAX14920 Hoja de datos, Descripción, Manual

EVALUATION KIT AVAILABLE
MAX14920 / MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
General Description
The MAX14920/MAX14921 battery measurement analog
front-end devices accurately sample cell voltages and
provide level shifting for primary/secondary battery packs
up to 16 cells/+65V (max). The MAX14920 monitors up
to 12 cells, while the MAX14921 monitors up to 16 cells.
Both devices simultaneously sample all cell voltages,
allowing accurate state-of-charge and source-resistance
determination. All cell voltages are level shifted to ground
reference with unity gain, simplifying external ADC data
conversion.
The devices have a low-noise, low-offset amplifier that
buffers differential voltages of up to +5V, allowing moni-
toring of all common lithium-ion (Li+) cell technologies.
The resulting cell voltage error is Q0.5mV.
The devices’ high accuracy make them ideal for monitoring
cell chemistries with very flat discharge curves, such as
lithium-metal phosphate.
Passive-cell balancing is supported by external FET
drivers. Integrated diagnostics in the devices allow
open-wire detection and undervoltage/overvoltage
alarms. The devices are controlled by a daisy-chainable
SPI interface.
The MAX14920 is available in a 64-pin (10mm x 10mm)
TQFP package with an exposed pad. The MAX14921 is
available in an 80-pin (12mm x 12mm) TQFP package.
Both devices are specified over the -40°C to +85°C
extended temperature range.
Applications
Industrial Battery Backup Systems
Telecom Battery Backup Systems
Energy Storage Packs
e-Transportation Energy Packs
Benefits and Features
S High Accuracy
±0.5mV (max) Cell Voltage
Simultaneous Cell Voltage Sampling
Self-Calibration
S Integrated Diagnostics
Open-Wire and Short Fault Detection
Undervoltage/Overvoltage Warning
Thermal Shutdown
S High Flexibility
SPI Interface
12-Cell and 16-Cell Versions
+6V Minimum (3 Cells) Operation
+0.5V to +4.5V Cell Voltage Range
Integrated Cell-Balancing FET Drivers
Integrated 5V LDO
S Low Power
1µA Shutdown Mode
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1µA/10µA Cell Current Draw
Ordering Information appears at end of data sheet.
Functional Diagram appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/MAX14920.related.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6496; Rev 0; 10/12
datasheet pdf - http://www.DataSheet4U.net/

1 page




MAX14920 pdf
MAX14920 / MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
DC ELECTRICAL CHARACTERISTICS (continued)
(VP = +65V, DGND = AGND, VL = VEN = +3.3V, VA = +5V, CSAMPLE = 1FF, TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Level-Shifting Delay Time
tLS_DELAY
Delay from SMPLB set to 1 or SAMPL
falling edge to shifting of all cell voltages
to ground and available for reading
25 50 Fs
AOUT Voltage-Droop Time
T_ Settling Time
T_ Turn-On Delay Time
VP Settling Time
Self-Calibration Time
tDROOP
Droop to -1mV (Figure 2)
1
ms
Measured between T_ input selection
tTS and AOUT settling to +1mV accuracy,
CLOAD = 100pF, SC2 = 1
5 Fs
tTD 0.2 Fs
Measured between VP/12 (MAX14920),
tVPS
VP/16 (MAX14921) input selection and
AOUT, settling to 2.5%,
CLOAD = 100pF, SC3 = 1
25 60 Fs
8 ms
THERMAL DETECTION
Thermal Shutdown
Thermal-Shutdown Hysteresis
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+140
15
°C
°C
SPI TIMINGS (Figure 3)
SDI to SCLK Setup
SDI to SCLK Hold
SCLK to SDO Valid
CS Fall to SDO Enable
CS Rise to SDO Disable
CS Pulse Width
CS Fall to SCLK Rise Setup
CS Rise to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Period
tDS
tDH
tDO
tDV
tTR
tCSW
tCSS
tCSH
tCH
tCL
tCP
50 ns
12 ns
100 ns
100 ns
80 ns
50 ns
100 ns
0 ns
65 ns
65 ns
208 ns
Note 2: All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
Note 3: Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921).
Note 4: Output error VO_ERR is the difference between the input cell difference voltage (VD = VCV(n) - VCV(n - 1)) and the
output voltage VAOUT. Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). Output error depends on buffer ampli-
fier errors and parasitic capacitance charge injection error. Since parasitic capacitance error is PCB dependent, output
error is guaranteed by design for a sampling capacitor of 1FF and parasitic capacitance less than 2.5pF on CTn (see the
Measurement Accuracy section for a detailed explanation).
Note 5: Buffer amplifier self-calibrates its offset at power-up and every time it is requested. Due to possible thermal drift after
power-up phase, it is suggested to run self-calibration on a regular basis to get best performance
(see the Buffer Amplifier Offset Calibration section for a detailed explanation).
Note 6: Amplifier error is the sum of all errors including amplifier offset and gain error.
Maxim Integrated
  5
datasheet pdf - http://www.DataSheet4U.net/

5 Page





MAX14920 arduino
MAX14920 / MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
PIN
MAX14920
(64 TQFP-EP)
MAX14921
(80 TQFP)
21 37
22 38
23 39
24 40
25 41
26 42
27 43
28 44
29 45
30 46
31 47
32 48
33 49
34 50
35 51
Pin Description (continued)
NAME
FUNCTION
CT11
CB11
CV10
BA10
CT10
CB10
CV9
BA9
CT9
CB9
CV8
BA8
CT8
CB8
CV7
Sampling Capacitor 11 High Terminal. CT11 internally connects to CV11 when
SAMPL is logic-high. Connect a 1FF capacitor between CT11 and CB11. Leave
CT11 unconnected if not used.
Sampling Capacitor 11 Low Terminal. CB11 internally connects to CV10 when
SAMPL is logic-high. Connect a 1FF capacitor between CT11 and CB11. Leave
CB11 unconnected if not used.
Cell Voltage Input 10. Connect CV10 to cell anode/cathode. Connect CV10 to the
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 10. Connect BA10 to the gate of the external
n-channel FET. Leave BA10 unconnected if not used.
Sampling Capacitor 10 High Terminal. CT10 internally connects to CV10 when
SAMPL is logic-high. Connect a 1FF capacitor between CT10 and CB10. Leave
CT10 unconnected if not used.
Sampling Capacitor 10 Low Terminal. CB10 internally connects to CV9 when
SAMPL is logic-high. Connect a 1FF capacitor between CT10 and CB10. Leave
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CB10 unconnected if not used.
Cell Voltage Input 9. Connect CV9 to cell anode/cathode. Connect CV9 to the
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 9. Connect BA9 to the gate of the external
n-channel FET. Leave BA9 unconnected if not used.
Sampling Capacitor 9 High Terminal. CT9 internally connects to CV9 when
SAMPL is logic-high. Connect a 1FF capacitor between CT9 and CB9. Leave CT9
unconnected if not used.
Sampling Capacitor 9 Low Terminal. CB9 internally connects to CV8 when
SAMPL is logic-high. Connect a 1FF capacitor between CT9 and CB9. Leave CB9
unconnected if not used.
Cell Voltage Input 8. Connect CV8 to cell anode/cathode. Connect CV8 to the
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 8. Connect BA8 to the gate of the external
n-channel FET. Leave BA8 unconnected if not used.
Sampling Capacitor 8 High Terminal. CT8 internally connects to CV8 when
SAMPL is logic-high. Connect a 1FF capacitor between CT8 and CB8. Leave CT8
unconnected if not used.
Sampling Capacitor 8 Low Terminal. CB8 internally connects to CV7 when
SAMPL is logic-high. Connect a 1FF capacitor between CT8 and CB8. Leave CB8
unconnected if not used.
Cell Voltage Input 7. Connect CV7 to cell anode/cathode. Connect CV7 to the
highest voltage of the battery cell stack if not used.
Maxim Integrated
  11
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