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Número de pieza UM10562
Descripción LPC408x/407x User manual
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UM10562
LPC408x/407x User manual
Rev. 1 — 13 September 2012
User manual
Document information
Info Content
Keywords
LPC4088FBD208, LPC4088FET208, LPC4088FET180,
LPC4088FBD144, LPC4078FBD208, LPC4078FET208,
LPC4078FBD144, LPC4078FBD80, LPC4076FET180, LPC4074FBD144,
LPC4074FBD80, ARM, ARM Cortex-M4, 32-bit, USB, Ethernet, LCD,
CAN, I2C, I2S, Flash, EEPROM, Microcontroller
Abstract
LPC408x/407x user manual
http://www.DataSheet4U.net/
datasheet pdf - http://www.DataSheet4U.net/

1 page




UM10562 pdf
NXP Semiconductors
UM10562
Chapter 1: Introductory information
Supports up to 24-bit true-color mode.
Serial interfaces:
Ethernet MAC with MII/RMII interface and dedicated DMA controller.
USB 2.0 full-speed controller that can be configured for either device, Host, or
OTG operation with an on-chip PHY for device and Host functions and a dedicated
DMA controller. USB Host and OTG are not available on LPC4074 devices.
Five UARTs with fractional baud rate generation, internal FIFOs, IrDA, DMA
support, and RS-485/EIA-485 support on most LPC408x/407x devices. UART1
also has a full set of modem handshaking signals. UART4 includes a synchronous
mode and a Smart Card mode supporting ISO 7816-3. UART4 is not available on
LPC4074 devices.
Three SSP controllers with FIFO and multi-protocol capabilities. The SSP
interfaces can be used with the GPDMA controller.
Three enhanced I2C-bus interfaces, one with an open-drain output supporting the
full I2C specification and Fast mode Plus with data rates of 1Mbit/s, two with
standard port pins. Enhancements include multiple address recognition and
monitor mode.
Two-channel CAN controller.
I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I2S interface can be used with the GPDMA. The I2S interface supports
3-wire data transmit and receive or 4-wire combined transmit and receive
connections, as well as master clock output.
SPIFI (SPI Flash Interface). Thishttp://www.DataSheet4U.net/ interface uses an SPI bus superset with 4 data
lines to access off-chip Quad SPI Flash memory at a much higher rate than is
possible using standard SPI or SSP interfaces. The SPIFI function allows memory
mapping the contents of the off-chip SPI Flash memory such that it can be
executed as if it were on-chip code memory. Supports SPI memories with 1 or 4
data lines.
Other peripherals:
SD card interface that also supports MMC cards. The SD card interface is not
available on LPC4074 devices.
General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open
drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast
access, and support Cortex-M4 bit-banding. GPIOs can be accessed by the
General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate
an interrupt. There are 165 GPIOs on 208-pin packages, 141 GPIOs on 180-pin
packages, and 109 GPIOs on 144-pin packages.
12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support.
Dual analog comparator with multiple selectable inputs, selectable internal
reference voltages, and versatile interrupt generation. The comparators are not
available on LPC4074 devices.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
5 of 942
datasheet pdf - http://www.DataSheet4U.net/

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UM10562 arduino
NXP Semiconductors
UM10562
Chapter 1: Introductory information
This architecture allows the possibility for CPU and DMA accesses to be separated in
such a way that there are few or no delays for the bus masters. It also allows separation of
data for different peripherals functions, in order to improve system performance. For
example, LCD DMA can be occurring in one SRAM while Ethernet DMA is occurring in
another, all while the CPU is using the Main SRAM for data and/or instruction access.
1.10 On-chip EEPROM
The LPC408x/407x contains up to 4,032 bytes of on-chip EEPROM memory. The
EEPROM is accessible only by the CPU.
http://www.DataSheet4U.net/
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
11 of 942
datasheet pdf - http://www.DataSheet4U.net/

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