PDF UM10360 Data sheet ( Hoja de datos )

Número de pieza	UM10360
Descripción	LPC17xx User manual
Fabricantes	NXP Semiconductors
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No Preview Available ! UM10360 LPC17xx User manual Rev. 01 — 4 January 2010 User manual Document information Info Content Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller Abstract LPC17xx user manual http://www.DataSheet4U.net/ datasheet pdf - http://www.DataSheet4U.net/ 1 page NXP Semiconductors UM10360 Chapter 1: LPC17xx Introductory information UM10360_1 User manual – I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S interface can be used with the GPDMA. The I2S interface supports 3-wire data transmit and receive or 4-wire combined transmit and receive connections, as well as master clock output. • Other peripherals: – 70 (100 pin package) or 52 (80-pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access, and support Cortex-M3 bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate an interrupt. – 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. – 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. – Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. – One motor control PWM with support for three-phase motor control. – Quadrature encoder interface that can monitor one external quadrature encoder. – One standard PWM/timer block with external count input. – Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a dedicated RTC oscillator. The RTChttp://www.DataSheet4U.net/ block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off. Battery power can be supplied from a standard 3 V Lithium button cell. The RTC will continue working when the battery voltage drops to as low as 2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode. – Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. – Cortex-M3 system tick timer, including an external clock input option. – Repetitive interrupt timer provides programmable and repeating timed interrupts. • Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire Trace Port options. • Emulation trace module supports real-time trace. • Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. • Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C. • Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources. • Non-maskable Interrupt (NMI) input. • Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, or the USB clock. • The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes. Rev. 01 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 5 of 835 datasheet pdf - http://www.DataSheet4U.net/ 5 Page NXP Semiconductors 10. Block diagram UM10360 Chapter 1: LPC17xx Introductory information JTAG interface Debug Port Ethernet PHY USB interface interface TEST/DEBUG INTERFACE ARM Cortex-M3 I-code D-code System bus bus bus DMA controller Ethernet 10/100 MAC Multilayer AHB Matrix APB slave group 0 SSP1 UARTs 0 & 1 CAN 1 & 2 I2C 0 & 1 SPI0 Capture/compare timers 0 & 1 Watchdog timer PWM1 12-bit ADC Pin connect block GPIO interrupt control 32 kHz oscillator Real Time Clock Vbat ultra-low power regulator Backup registers (20 bytes) RTC Power Domain AHB to APB bridge AHB to APB bridgehttp://www.DataSheet4U.net/ USB device, host, OTG clocks and controls internal power clock generation, CLK power control, OUT and other system functions voltage regulator Vdd Flash Accelerator Flash 512 kB SRAM 32 kB SRAM 16 kB ROM 8 kB SRAM 16 kB HS GPIO DMAC USB Ethernet regs regs regs APB slave group 1 SSP0 UARTs 2 & 3 I2S I2C2 Capture/compare timers 2 & 3 Repetitive interrupt timer External interrupts DAC System control Motor control PWM Quadrature encoder Note: shaded peripheral blocks support General Purpose DMA Fig 2. LPC1768 block diagram, CPU and buses UM10360_1 User manual Rev. 01 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 11 of 835 datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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