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PDF IDT70V07L Data sheet ( Hoja de datos )
| Número de pieza | IDT70V07L | |
| Descripción | HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
IDT70V07S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Commercial: 25/35/55ns (max.)
• Low-power operation
— IDT70V07S
Active: 450mW (typ.)
Standby: 5mW (typ.)
— IDT70V07L
Active: 450mW (typ.)
Standby: 5mW (typ.)
• IDT70V07 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• LVTTL-compatible, single 3.3V (±0.3V) power supply
• Available in 68-pin PGA, 68-pin PLCC, and a 64-pin
TQFP
DESCRIPTION:
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static
RAM. The IDT70V07 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
FUNCTIONAL BLOCK DIAGRAM
OEL
WCEL
R/ L
OER
WCER
R/ R
I/O0L- I/O7L
(1,2)
BUSYL
A14L
A0L
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
WR/ L
15
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
15
CER
WOER
R/ R
SEML
(2)
INTL
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.37
I/O0R-I/O7R
BUSYR(1,2)
A14R
A0R
SEMR
(2)
INTR
2943 drw 01
OCTOBER 1996
DSC-2943/3
1
1 page  
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V ± 0.3V)
IDT70V07S
IDT70V07L
Symbol
|ILI|
|ILO|
Parameter
Input Leakage Current(1)
Output Leakage Current
Test Conditions
VCC = 3.6V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
Min.
—
—
Max.
10
10
Min.
—
—
Max.
5
5
VOL Output Low Voltage
IOL = 4mA
— 0.4 — 0.4
VOH Output High Voltage
IOH = -4mA
2.4 — 2.4 —
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
Unit
µA
µA
V
V
2943 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 3.3V ± 0.3V)
Symbol
Parameter
ICC Dynamic Operating
Current
(Both Ports Active)
ISB1 Standby Current
(Both Ports — TTL
Level Inputs)
ISB2 Standby Current
Test
Condition
CE = VIL, Outputs Open
SEM = VIH
f = fMAX(3)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
CE CE"A" = VIL and "B" = VIH(5)
70V07X25
70V07X35 70V07X55
Version Typ.(2)
COM’L. S 100
L 100
Max. Typ.(2)
170 90
140 90
Max. Typ.(2)
140 90
120 90
Max. Unit
140 mA
120
COM’L. S 14
L 12
30 12
24 10
30 12
24 10
30 mA
24
COM’L. S 50
95 45
87 45 87 mA
(One Port — TTL
Active Port Outputs Open,
Level Inputs)
f = fMAX(3)
SEMR = SEML = VIH
ISB3 Full Standby Current Both Ports CEL and
(Both Ports — All
CER > VCC - 0.2V
L 50
85 45
75 45 75
COM’L. S 1.0
L 0.2
6 1.0
3 0.2
6 1.0
3 0.2
6 mA
3
CMOS Level Inputs)
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
ISB4 Full Standby Current CE"A" < 0.2V and
(One Port — All
CE"B" > VCC - 0.2V(5)
CMOS Level Inputs) SEMR = SEML > VCC - 0.2V
COM’L. S 60
L 60
90 55
80 55
85 55
74 55
85 mA
74
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open
f = fMAX(3)
NOTES:
2943 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.37 5
5 Page 
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (2,4,5)
ADDR"A"
WR/ "A"
DATAIN "A"
tAPS(1)
ADDR"B"
BUSY"B"
DATAOUT "B"
tWC
MATCH
tWP
tDW
VALID
tDH
MATCH
tBDA
tWDD
tDDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
tBDD
VALID
2943 drw 13
TIMING WAVEFORM OF WRITE WITH BUSY
WR/ "A"
BUSY"B"
tWP
tWB( 3 )
WR/ "B"
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes High.
tWH ( 1 )
2943 drw 14
6.37 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet IDT70V07L.PDF ] | |
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