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PDF VT6508 Data sheet ( Hoja de datos )
| Número de pieza | VT6508 | |
| Descripción | 8 RMII PORTS OF 10/100BASE-T/TX ETHERNET SWITCH CONTROLLER | |
| Fabricantes | VIA | |
| Logotipo |  |
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VIA Technologies, Inc.
Preliminary VT6508 Datasheet
VT6508
http://www.DataSheet4U.net/
8 RMII PORTS OF 10/100BASE-T/TX
ETHERNET SWITCH CONTROLLER
REVISION ‘D’ DATASHEET
(Preliminary)
ISSUE 1: Nov 23, 1999
VIA Technologies, Inc.
1
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1 page  
VIA Technologies, Inc.
Preliminary VT6508 Datasheet
REVERSION HISTORY
Reversion
V0.01
Date
11/23/1999
Reason for change
First release version
By
Murphy Chen
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5 Page 
VIA Technologies, Inc.
Preliminary VT6508 Datasheet
PIN DESCRIPTIONS
No. Name
See Fig. 2
See Fig. 2
See Fig. 2
See Fig. 2
See Fig. 2
See Fig. 2
CSDV[7:0]
RXD0[7:0]
RXD1[7:0]
TXEN[7:0]
TXD0[7:0]
TXD1[7:0]
See Fig. 2 SA[15:1]
See Fig. 2 SOE
Type
I
I
I
O
O
O
O
O
Description
RMII interface
Carries sense and data valid from port 7 to port 0 :
Receive data zero from port 7 to port 0 :
Receive data one from port 7 to port 0 :
Transmit enable from port 7 to port 0 :
Transmit data zero from port 7 to port 0 :
Transmit data one from port 7 to port 0 :
SRAM Interface
SRAM Address Bus:
15-bit SDRAM data bus. These signals connect directly to the address
input of the SDRAM devices.
Output Enable
See Fig. 2 SWE
O SRAM Write Enable
See Fig. 2 SADS
O Synchronous Processor Address Status
See Fig. 2 SD[31:0]
See Fig. 2 EEC/LEDC
See Fig. 2 EEIO/LEDIO
See Fig. 2
See Fig. 2
See Fig. 2
See Fig. 2
MDC
MDIO
RCLK50
SCLK
See Fig. 2 RESET
I/O SRAM Data:
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32-bit SRAM data bus. These signals connect directly to the data
input/output pins of the SRAM devices.
Miscellaneous Interface
O Serial EEPROM Interface Clock (if strapping SD25 is default high)
The on-board EEPROM device address must be 1010 001 XXXXXXXX.
Serial LED Serial-Out Clock (if strapping SD25 is low)
The LEDC is 1MHz and has a burst per 50ms.
I/O Serial EEPROM Interface Data (if strapping SD25 is default high)
Serial LED Serial-Out Data Output (if strapping SD25 is low)
O Management Interface (MI) Clock Output
I/O Management Interface (MI) Data I/O
I 50MHz Main Reference Clock
I SRAM Reference Clock
The suggested clock rate is 83MHz or more high for non-blocking
requirement.
I SYSTEM RESET
Power Supply & Ground
See Fig. 2 VDD
See Fig. 2 VCC
P
P
Positive 3.3V supply to the core digital logic.
Positive 3.3V supply to all I/O pads.
-11-
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| PDF Descargar | [ Datasheet VT6508.PDF ] | |
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