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PDF FDC655BN Data sheet ( Hoja de datos )

Número de pieza FDC655BN
Descripción PowerTrench MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FDC655BN Hoja de datos, Descripción, Manual

April 2005
FDC655BN
Single N-Channel, Logic Level, PowerTrench® MOSFET
Features
6.3 A, 30 V.
RDS(ON) = 25 m@ VGS = 10 V
RDS(ON) = 33 m@ VGS = 4.5 V
Fast switching
Low gate charge
High performance trench technology for extremely low Rdson
General Description
This N-Channel Logic Level MOSFET is produced using Fair-
child Semiconductor’s advanced PowerTrench process that has
been especially tailored to minimized on-state resistance and
yet maintain superior switching performance.
These devices are well suited for low voltage and battery pow-
ered applications where low in-line power loss and fast switch-
ing are required.
S
D
D 55B
SuperSOT-6TM
G
D
D
16
25
34
Absolute Maximum Ratings T = 25°C unless otherwise notedA
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Symbol
Parameter
VDSS
VGSS
ID
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
(Note 1a)
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ, TSTG Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
Ratings
30
±20
6.3
20
1.6
0.8
– 55 to +150
78
30
Package Marking and Ordering Information
Device Marking
.55B
Device
FDC655BN
Reel Size
7’’
Tape width
8mm
Units
V
V
A
W
°C
°C/W
°C/W
Quantity
3000 units
©2005 Fairchild Semiconductor Corporation
FDC655BN Rev. C(W)
1
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FDC655BN pdf
Typical Characteristics
VDS
VGS
RGE
L
DUT
0V
VGS
tp
vary tP to obtain
required peak IAS
IAS
0.01
+
VDD
Figure 12. Unclamped Inductive
Load Test Circuit
tP
IAS
BVDSS
VDS
VDD
tAV
Figure 13. Unclamped Inductive
Waveforms
Drain Current
Same type as DUT
+
10V
50k
- 10 F
1F
VGS
Ig(REF)
DUT
+
VDD
10V
VGS
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QG(TOT)
QGS
QGD
Figure 14. Gate Charge Test Circuit
Charge, (nC)
Figure 15. Gate Charge Waveform
VDS
VGS
RGEN
VGS Pulse Width 1µs
Duty Cycle 0.1%
RL
DUT
+
VDD
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
0V
VGS
10%
0V
10%
10%
50%
Pulse Width
90%
50%
Figure 16. Switching Time
Test Circuit
Figure 17. Switching Time Waveforms
FDC655BN Rev. C(W)
5
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