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PDF BU-61580 Data sheet ( Hoja de datos )

Número de pieza BU-61580
Descripción (BU-61580 - BU-61585) MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT
Fabricantes DDC 
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BU-65170/61580 and BU-61585
MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT,
ADVANCED COMMUNICATION ENGINE (ACE)
ACE User’s Guide
Also Available
DESCRIPTION
DDC's BU-65170, BU-61580 and
BU-61585 Bus Controller / Remote
Terminal / Monitor Terminal
(BC/RT/MT)
Advanced
Communication Engine (ACE) termi-
nals comprise a complete integrated
interface between a host processor
and a MIL-STD-1553 A and B or
STANAG 3838 bus.
configured as 12K x 16 or 8K x 17.
The 8K x 17 RAM feature provides
capability for memory integrity check-
ing by implementing RAM parity gen-
eration and verification on all access-
es. To minimize board space and
“glue” logic, the ACE provides ultimate
flexibility in interfacing to a host
processor and internal/external RAM.
The ACE series is packaged in a 1.9 -
square-inch, 70-pin, low-profile,
cofired MultiChip Module (MCM)
ceramic package that is well suited for
applications with stringent height
requirements.
The BU-61585 ACE integrates dual
transceiver, protocol, memory man-
agement, processor interface logic,
and a total of 12K words of RAM in a
choice of DIP or flat pack packages.
The BU-61585 requires +5 V power
and either -15 V or -12 V power.
The BU-61585 internal RAM can be
The advanced functional architecture
of the ACE terminals provides soft-
ware compatibility to DDC's
Advanced Integrated Multiplexer (AIM)
series hybrids, while incorporating a
multiplicity of architectural enhance-
ments. It allows flexible operation
while off-loading the host processor,
ensuring data sample consistency,
and supports bulk data transfers.
The ACE hybrids may be operated at
either 12 or 16 MHz. Wire bond
options allow for programmable RThttp://www.DataSheet4U.net/
address (hardwired is standard) and
external transmitter inhibit inputs.
FEATURES
Fully Integrated MIL-STD-1553
Interface Terminal
Flexible Processor/Memory
Interface
Standard 4K x 16 RAM and
Optional 12K x 16 or 8K x 17 RAM
Available
Optional RAM Parity
Generation/Checking
Automatic BC Retries
Programmable BC Gap Times
BC Frame Auto-Repeat
Flexible RT Data Buffering
Programmable Illegalization
Selective Message Monitor
Simultaneous RT/Monitor Mode
CH. A
TX/RX_A
TRANSCEIVER
A
TX/RX_A
TX/RX_B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
*SHARED
RAM
DATA BUS
ADDRESS BUS
DATA
BUFFERS
ADDRESS
BUFFERS
D15-D0
A15-A0
PROCESSOR
DATA BUS
PROCESSOR
ADDRESS BUS
CH. B
TRANSCEIVER
B
RT ADDRESS
MISCELLANEOUS
TX/RX_B
RTAD4-RTAD0, RTADP
INCMD
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
PROCESSOR
AND
MEMORY
CONTROL
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
INT INTERRUPT
REQUEST
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
FIGURE 1. ACE BLOCK DIAGRAM
© 1992, 1999 Data Device Corporation
datasheet pdf - http://www.DataSheet4U.net/

1 page




BU-61580 pdf
The J´ chip consists of a dual encoder/decoder, complete proto-
col for Bus Controller (BC), 1553A/B/McAir Remote Terminal
(RT), and Monitor (MT) modes; memory management and inter-
rupt logic; a flexible, buffered interface to a host processor bus
and optional external RAM; and 4K words of on-chip RAM.
Reference the region within the dotted line of FIGURE 1. Besides
realizing all the protocol, memory management, and interface
functions of the earlier AIM-HY'er series, the J´ chip includes a
large number of enhancements to facilitate hardware and soft-
ware design, and to further off-load the 1553 terminal's host
processor.
DECODERS
The default mode of operation for the BU-65170 RT and BU-
61580 BC/RT/MT requires a 16 MHz clock input. If needed, a
software programmable option allows the device to be operated
from a 12 MHz clock input. Most current 1553 decoders sample
using a 10 MHz or 12 MHz clock. In the 16 MHz mode (default
following a hardware or software reset), the ACE decoders sam-
ple 1553 serial data using the 16 MHz clock. In the 12 MHz
mode, the decoders sample using both clock edges; this pro-
vides a sampling rate of 24 MHz. The faster sampling rate for the
J´ chip’s Manchester II decoders provides superior performance
in terms of bit error rate and zero-crossing distortion tolerance.
For interfacing to fiber optic transceivers for MIL-STD-1773 appli-
cations, a transceiverless version of the J´ chip, the BU-65620,
can be used. These versions provide a pin-programmable option
for a direct interface to the single-ended outputs of a fiber optic
receiver. No external logic is needed.
put pin (INT) has three software programmable modes of oper-
ation: a pulse, a level output cleared under software control, or a
level output automatically cleared following a read of the
Interrupt Status Register.
Individual interrupts are enabled by the Interrupt Mask Register.
The host processor may easily determine the cause of the inter-
rupt by using the Interrupt Status Register. The Interrupt Status
Register provides the current state of the interrupt conditions.
The Interrupt Status Register may be updated in two ways. In the
standard interrupt handling mode, a particular bit in the Interrupt
Status Register will be updated only if the condition exists and
the corresponding bit in the Interrupt Mask Register is enabled.
In the enhanced interrupt handling mode, a particular bit in the
Interrupt Status Register will be updated if the condition exists
regardless of the contents of the corresponding Interrupt Mask
Register bit. In any case, the respective Interrupt Mask Register
bit enables an interrupt for a particular condition.
ADDRESSING, INTERNAL REGISTERS, AND
MEMORY MANAGEMENT
The software interface of the BU-65170/61580 to the host
processor consists of 17 internal operational registers for normal
operation, an additional 8 test registers, plus 64K x 16 of shared
memory address space. The BU-65170/61580's 4K x 16 of inter-
nal RAM resides in this address space. Reference TABLE 2 and
24.
Definition of the address mapping and accessibility for the ACE's
17 non-test registers, and the test registers, is as follows:
TIME TAGGING
The ACE includes an internal read/writable Time Tag Register.
This register is a CPU read/writable 16-bit counter with a pro-
grammable resolution of either 2, 4, 8, 16, 32, or 64 µs per LSB.
Also, the Time Tag Register may be clocked from an external
oscillator. Another option allows software-controlled increment-
ing of the Time Tag Register. This supports self-testing for the
Time Tag Register. For each message processed, the value of
the Time Tag register is loaded into the second location of the
respective descriptor stack entry (“TIME TAG WORD”) for both
BC and RT modes.
Additional provided options will: clear the Time Tag Register fol-
lowing a Synchronize (without data) mode command or load the
Time Tag Register following a Synchronize (with data) mode
command; enable an interrupt request and a bit setting in the
Interrupt Status Register when the Time Tag Register rolls over
from 0000 to FFFF. Assuming the Time Tag Register is not
loaded or reset, this will occur at approximately 4-second time
intervals, for 64 µs/LSB resolution, down to 131 ms intervals, for
2 µs/LSB resolution.
Another programmable option for RT mode is the automatic
clearing of the Service Request Status Word bit following the
ACE's response to a Transmit Vector Word mode command.
INTERRUPTS
The ACE series components provide many programmable
options for interrupt generation and handling. The interrupt out-
Interrupt Mask Register is used to enable and disable interrupt
requests for various conditions.http://www.DataSheet4U.net/
Configuration Registers #1 and #2 are used to select the BU-
61580's mode of operation, and for software control of RT Status
Word bits, Active Memory Area, BC Stop-on-Error, RT Memory
Management mode selection, and control of the Time Tag oper-
ation.
Start/Reset Register is used for “command” type functions,
such as software reset, BC/MT Start, Interrupt Reset, Time Tag
Reset, and Time Tag Register Test. The Start/Reset Register
includes provisions for stopping the BC in its auto-repeat mode,
either at the end of the current message or at the end of the cur-
rent BC frame.
BC/RT Command Stack Pointer Register allows the host CPU
to determine the pointer location for the current or most recent
message when the BU-61580 is in BC or RT modes.
BC Control Word/RT Subaddress Control Word Register: In
BC mode, it allows host access to the current, or most recent BC
Control Word. The BC Control Word contains bits that select the
active bus and message format, enable off-line self-test, mask-
ing of Status Word bits, enable retries and interrupts, and spec-
ify MIL-STD-1553A or -1553B error handling. In RT mode, this
register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message. The read/write accessibility
can be used as an aid for testing the ACE.
Data Device Corporation
www.ddc-web.com
5
BU-65170/61580/61585
H1 web-09/02-0
datasheet pdf - http://www.DataSheet4U.net/

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BU-61580 arduino
BUS CONTROLLER (BC) ARCHITECTURE
The BC protocol of the BU-61580 implements all MIL-STD-
1553B message formats. Message format is programmable on a
message-by-message basis by means of bits in the BC Control
Word and the T/R bit of the Command Word for the respective
message. The BC Control Word allows 1553 message format,
1553A/B type RT, bus channel, self-test, and Status Word mask-
ing to be specified on an individual message basis. In addition,
automatic retries and/or interrupt requests may be enabled or
disabled for individual messages. The BC performs all error
checking required by MIL-STD-1553B. This includes validation of
response time, sync type and sync encoding, Manchester II
encoding, parity, bit count, word count, Status Word RT Address
field, and various RT-to-RT transfer errors. The BU-61580's BC
response timeout value is programmable with choices of 18, 22,
50, and 130 µs. The longer response timeout values enable
operation over long buses and/or the use of repeaters.
FIGURE 2 illustrates BC intermessage gap and frame timing.
The BU-61580 may be programmed to process BC frames of up
to 512 messages with no processor intervention. It is possible to
program for either single frame or frame auto-repeat operation.
In the auto-repeat mode, the frame repetition rate may be con-
trolled either internally, using a programmable BC frame timer, or
from an external trigger input. The internal BC frame time is pro-
grammable up to 6.55 seconds in increments of 100 µs. In addi-
tion to BC frame time, intermessage gap time, measured from
the start of the current message to the start of the subsequent
message, is programmable on an individual message basis. The
time between individual successive messages is programmable
up to 65.5 ms, in increments of 1 µs.
BC MEMORY ORGANIZATION
TABLE 25 illustrates a typical memory map for BC mode. It is
important to note that the only fixed locations for the BU-61580
in the Standard BC mode are for the two Stack Pointers (address
locations 0100 (hex) and 0104) and for the two Message Count
locations (0101 and 0105). Enabling the Frame Auto-Repeat
mode will reserve four more memory locations for use in the
Enhanced BC mode; these locations are for the two Initial Stack
Pointers (address locations 102 (hex) and 106) and for the Initial
Message Count locations (103 and 107). The user is free to
TABLE 25. TYPICAL BC MEMORY ORGANIZATION
(SHOWN FOR 4K RAM)
ADDRESS
(HEX)
DESCRIPTION
0000-00FF
Stack A
0100
Stack Pointer A (fixed location)
0101
Message Count A (fixed location)
0102
Initial Stack Pointer A (see note) (Auto-Frame Repeat
Mode)
0103
Initial Message Count A (see note)
(Auto-Frame Repeat Mode)
0104
Stack Pointer B
0105
Message Count B
0106
Initial Stack Pointer B (see note)
(Auto-Frame Repeat Mode)
0107
Initial Message Count B (see note)
(Auto-Frame Repeat Mode)
0108-012D
Message Block 0
012E-0153
Message Block 1
0154-0179
Message Block 2
••
••
••
0ED6-0EFB
Message Block 93
0EFC-0EFF
Not Used
0F00-0FFF
Stack B
Note: Used only in the Enhanced BC mode with Frame Auto-Repeat enabled.
http://www.DataSheet4U.net/
locate the Stack and BC Message Blocks anywhere else within
the 64K (4K internal) shared RAM address space.
For simplicity of illustration, assume the allocation of the maxi-
mum length of a BC message for each message block in the typ-
ical BC memory map of TABLE 25. The maximum size of a BC
message block is 38 words, for an RT-to-RT transfer of 32 Data
Words (Control + 2 Commands + Loopback + 2 Status Words +
32 Data Words). Note, however, that this example assumes the
disabling of the 256-word boundaries.
MESSAGE
GAP TIME
FOR MESSAGE NO. 1
INTERMESSAGE GAP TIME
MESSAGE NO. 1
MESSAGE NO. 2
BC FRAME TIME
Data Device Corporation
www.ddc-web.com
FIGURE 2. BC MESSAGE GAP AND FRAME TIMING
11
MESSAGE NO. 1
BU-65170/61580/61585
H1 web-09/02-0
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