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PDF VND7020AJ-E Data sheet ( Hoja de datos )

Número de pieza VND7020AJ-E
Descripción Double channel high-side driver
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! VND7020AJ-E Hoja de datos, Descripción, Manual

VND7020AJ-E
Double channel high-side driver with MultiSense analog feedback
for automotive applications
Datasheet production data
Features
Max transient supply voltage
VCC
Operating voltage range
VCC
Typ. on-state resistance (per Ch) RON
Current limitation (typ)
ILIMH
Stand-by current (max)
ISTBY
40 V
4 to 28 V
22 mΩ
63 A
0.5 µA
General
– Double channel smart high side driver with
MultiSense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS
outputs
MultiSense diagnostic functions
– Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
TCHIP device temperature
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
– Sense enable/disable
Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Configurable latch-off on overtemperature
or power limitation with dedicated fault
reset pin
– Loss of ground and loss of VCC
– Reverse battery with external components
– Electrostatic discharge protection
1PXFS440
("1($'5
Applications
All types of Automotive resistive, inductive and
capacitive loads
Specially intended for automotive turn
indicators (up to 2x P27W or SAE1156 and
R5W paralleled or LED rear combinations)
Description
The VND7020AJ-E is a double channel high-side
driver manufactured using ST proprietary
VIPower® M0-7 technology and housed in
PowerSSO-16 package. The device is designedhttp://www.DataSheet4U.net/
to drive 12 V automotive grounded loads through
a 3 V and 5 V CMOS-compatible interface,
providing protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
September 2012
This is information on a product in full production.
Doc ID 018795 Rev. 4
1/43
www.st.com
1
datasheet pdf - http://www.DataSheet4U.net/

1 page




VND7020AJ-E pdf
VND7020AJ-E
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Switching time and Pulse skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MultiSense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Multisense timings (chip temperature and VCC sense mode) . . . . . . . . . . . . . . . . . . . . . . 19
TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) . . . . . . . . . . . 22
Latch functionality - behavior in hard short circuit condition . . . . . . . . . . . . . . . . . . . . . . . . 22
Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) 23
Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Multisense and diagnostic – block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Multisense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Analogue HSD – open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Maximum turn off current versus inductance(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . 35
PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . 35
Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . . 36
PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) . . . . . 36
Thermal fitting model of a double-channel HSD in PowerSSO-16(1) . . . . . . . . . . . . . . . . . 37
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PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 018795 Rev. 4
5/43
datasheet pdf - http://www.DataSheet4U.net/

5 Page





VND7020AJ-E arduino
VND7020AJ-E
Electrical specification
2. PowerMOS leakage included.
3. Parameter specified by design; not subject to production test.
Table 6. Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified)(1)
Symbol
Parameter
Test conditions Min. Typ. Max. Unit
td(on)
td(off)
Turn-on delay time at Tj = 25 °C
Turn-off delay time at Tj = 25 °C
RL = 4.3 Ω
10 60
10 40
(dVOUT/dt)on Turn-on voltage slope at Tj = 25 °C RL = 4.3 Ω
(dVOUT/dt)off Turn-off voltage slope at Tj = 25 °C
0.1 0.36
0.1 0.36
WON
Switching energy losses at turn-on
(twon)
RL = 4.3 Ω
— 0.38
WOFF
Switching energy losses at turn-off
(twoff)
RL = 4.3 Ω
— 0.39
tSKEW
Differential Pulse skew
(tPHL - tPLH) see Figure 4
RL = 4.3 Ω
-75 -25
1. See Figure 4: Switching time and Pulse skew
2. Parameter guaranteed by design and characterization; not subject to production test
120
µs
100
0.7
V/µs
0.7
0.49(2) mJ
0.54(2) mJ
25 µs
Table 7. Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions Min. Typ. Max. Unit
INPUT0,1 characteristics
VIL
IIL
VIH
IIH
VI(hyst)
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
VICL
Input clamp voltage
FaultRST characteristics
VFRL
IFRL
VFRH
IFRH
VFR(hyst)
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
VFRCL Input clamp voltage
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VIN = 0.9 V
VIN = 2.1 V
IIN = 1 mA
IIN = -1 mA
VIN = 0.9 V
VIN = 2.1 V
IIN = 1 mA
IIN = -1 mA
0.9
1
2.1
10
0.2
5.3 7.2
-0.7
V
µA
V
µA
V
V
0.9
1
2.1
10
0.2
5.3 7.5
-0.7
V
µA
V
µA
V
V
Doc ID 018795 Rev. 4
11/43
datasheet pdf - http://www.DataSheet4U.net/

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