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PDF PCAL9539A Data sheet ( Hoja de datos )
| Número de pieza | PCAL9539A | |
| Descripción | Low-voltage 16-bit I2C-bus and SMBus low power I/O port | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCAL9539A
Low-voltage 16-bit I2C-bus and SMBus low power I/O port with
interrupt and reset
Rev. 1 — 3 October 2012
Product data sheet
1. General description
The PCAL9539A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander
with interrupt and reset for I2C-bus/SMBus applications. NXP I/O expanders provide a
simple solution when additional I/Os are needed while keeping interconnections to a
minimum, for example, in ACPI power switches, sensors, push buttons, LEDs, fan control,
etc.
In addition to providing a flexible set of GPIOs, the wide VDD range of 1.65 V to 5.5 V
allows the PCAL9539A to interface with next-generation microprocessors and
microcontrollers where supply levels are dropping down to conserve power.
The PCAL9539A contains the PCA9539 register set of four pairs of 8-bit Configuration,
Input, Output, and Polarity Inversion registers, and additionally, the PCAL9539A has
Agile I/O, which are additional features specifically designed to enhance the I/O. These
additional features are: programmable output drive strength, latchable inputs,
programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register,
programmable open-drain or push-pull outputs.
The PCAL9539A is a pin-to-pin replacement to the PCA9539 and PCA9539A, however,
the PCAL9539A powers up with all I/O interrupts masked. This mask default allows for a
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board bring-up free of spurious interrupts at power-up.
The PCAL9539A open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I2C-bus. Thus, the PCAL9539A can
remain a simple slave device.
The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming
low device current.
The power-on reset sets the registers to their default values and initializes the device state
machine. In the PCAL9539A, the RESET pin causes the same reset/default I/O input
configuration to occur without de-powering the device, holding the registers and I2C-bus
state machine in their default state until the RESET input is once again HIGH. This input
requires a pull-up to VDD.
Two hardware pins (A0, A1) select the fixed I2C-bus address and allow up to four devices
to share the same I2C-bus/SMBus.
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1 page  
NXP Semiconductors
PCAL9539A
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Table 3.
Symbol
P1_6[3]
P1_7[3]
A0
SCL
Pin description …continued
Pin Type
TSSOP24 HWQFN24
19 16 I/O
20 17 I/O
21 18 I
22 19 I
SDA
23
20
I/O
VDD 24 21 power
Description
Port 1 input/output 6.
Port 1 input/output 7.
Address input 0. Connect directly to VDD or VSS.
Serial clock bus. Connect to VDD through a
pull-up resistor.
Serial data bus. Connect to VDD through a
pull-up resistor.
Supply voltage.
[1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
[2] Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance
inputs.
[3] Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance
inputs.
6. Functional description
Refer to Figure 1 “Block diagram of PCAL9539A”.
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6.1 Device address
slave address
1 1 1 0 1 A1 A0 R/W
fixed
hardware
selectable
002aah062
Fig 4. PCAL9539A device address
A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1)
or LOW (logic 0) to assign one of the four possible slave addresses. The last bit of the
slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Registers
6.2.1 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCAL9539A. The lower
three bits of this data byte state the operation (read or write) and the internal registers
PCAL9539A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
5 of 48
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5 Page 
NXP Semiconductors
PCAL9539A
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.9 Pull-up/pull-down selection register pair (48h, 49h)
The I/O port can be configured to have a pull-up or pull-down resistor by programming the
pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up
resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that
I/O pin. If the pull-up/pull-down feature is disconnected, writing to this register will have no
effect on I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k.
A register pair write is described in Section 7.1 and a register pair read is described in
Section 7.2.
Table 21.
Bit
Symbol
Default
Pull-up/pull-down selection port 0 register (address 48h)
765432
PUD0.7 PUD0.6 PUD0.5 PUD0.4 PUD0.3 PUD0.2
111111
1
PUD0.1
1
0
PUD0.0
1
Table 22.
Bit
Symbol
Default
Pull-up/pull-down selection port 1 register (address 49h)
765432
PUD1.7 PUD1.6 PUD1.5 PUD1.4 PUD1.3 PUD1.2
111111
1
PUD1.1
1
0
PUD1.0
1
6.2.10 Interrupt mask register pair (4Ah, 4Bh)
Interrupt mask registers are set to logic 1 upon power-on, disabling interrupts during
system start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0.
If an input changes state and the corresponding bit in the Interrupt mask register is set
to 1, the interrupt is masked and theh interruptt t p : / / w w pinw . D willa t a notS h e bee t 4 asserted.U . n e t / If the corresponding
bit in the Interrupt mask register is set to 0, the interrupt pin will be asserted.
When an input changes state and the resulting interrupt is masked (interrupt mask bit
is 1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted.
If the interrupt mask bit of an input that is currently the source of an interrupt is set to 1,
the interrupt pin will be de-asserted. A register pair write is described in Section 7.1 and a
register pair read is described in Section 7.2.
Table 23.
Bit
Symbol
Default
Interrupt mask port 0 register (address 4Ah) bit description
765432
M0.7
M0.6
M0.5
M0.4
M0.3
M0.2
111111
1
M0.1
1
0
M0.0
1
Table 24.
Bit
Symbol
Default
Interrupt mask port 1 register (address 4Bh) bit description
765432
M1.7
M1.6
M1.5
M1.4
M1.3
M1.2
111111
1
M1.1
1
0
M1.0
1
PCAL9539A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 October 2012
© NXP B.V. 2012. All rights reserved.
11 of 48
datashe
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