|
|
PDF PCAL6416A Data sheet ( Hoja de datos )
| Número de pieza | PCAL6416A | |
| Descripción | Low-voltage translating 16-bit I2C-bus/SMBus I/O expander | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PCAL6416A (archivo pdf) en la parte inferior de esta página. Total 54 Páginas | ||
|
No Preview Available !
PCAL6416A
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
with interrupt output, reset, and configuration registers
Rev. 3 — 24 December 2012
Product data sheet
1. General description
The PCAL6416A is a 16-bit general purpose I/O expander that provides remote I/O
expansion for most microcontroller families via the I2C-bus interface.
NXP I/O expanders provide a simple solution when additional I/Os are needed while
keeping interconnections to a minimum, for example, in battery-powered mobile
applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing
a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage
level to I/O devices operating at a different (usually higher) voltage level. The PCAL6416A
has built-in level shifting feature that makes these devices extremely flexible in mixed
signal environments where communication between incompatible I/O voltages is required.
Its wide VDD range of 1.65 V to 5.5 V on the dual power rail allows seamless
communications with next-generation low voltage microprocessors and microcontrollers
on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.
There are two supply voltages for PCAL6416A: VDD(I2C-bus) and VDD(P). VDD(I2C-bus)
provides the supply voltage for the interface at the master side (for example, a
microcontroller) and the VDD(P) provides the supply for core circuits and Port P. The
bidirectional voltage level translation in the PCAL6416A is provided through VDD(I2C-bus).
VDD(I2C-bus)
should
be
connected
to the
http://www.DataSheet4U.net/
VDD
of
the
external
SCL/SDA
lines.
This
indicates
the VDD level of the I2C-bus to the PCAL6416A, while the voltage level on Port P of the
PCAL6416A is determined by the VDD(P).
The PCAL6416A contains the PCA6416A register set of four pairs of 8-bit Configuration,
Input, Output, and Polarity Inversion registers and additionally, the PCAL6416A has
Agile I/O, which are additional features specifically designed to enhance the I/O. These
additional features are: programmable output drive strength, latchable inputs,
programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register,
programmable open-drain or push-pull outputs. The PCAL6416A is a pin-to-pin
replacement to the PCA6416A, however, the PCAL6416A powers up with all I/O interrupts
masked. This mask default allows for a board bring-up free of spurious interrupts at
power-up.
At power-on, the I/Os are configured as inputs. However, the system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity Inversion register, saving external
logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete
components.
datasheet pdf - http://www.DataSheet4U.net/
1 page  
NXP Semiconductors
5. Pinning information
5.1 Pinning
PCAL6416A
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
INT 1
VDD(I2C-bus) 2
RESET 3
P0_0 4
P0_1 5
P0_2 6
P0_3 7
P0_4 8
P0_5 9
P0_6 10
P0_7 11
VSS 12
PCAL6416APW
24 VDD(P)
23 SDA
22 SCL
21 ADDR
20 P1_7
19 P1_6
18 P1_5
17 P1_4
16 P1_3
15 P1_2
14 P1_1
13 P1_0
002aaf963
terminal 1
index area
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
1
2
3
4
5
6
PCAL6416AHF
18 ADDR
17 P1_7
16 P1_6
15 P1_5
14 P1_4
13 P1_3
Transparent top view
002aaf964
Fig 2. Pin configuration for TSSOP24
Fig 3.
The exposed center pad, if used, must be
connected only as a secondary ground or
must be left electrically open.
Pin configuration for HWQFN24
ball A1
index area
PCAL6416AEV
http://www.DataSheet4U.net/
12 345
A
B
C
D
E
Transparent top view
002aaf966
Fig 4. Pin configuration for VFBGA24
(3 mm 3 mm)
12
A P0_0 RESET
3
INT
4
SDA
5
SCL
B P0_2
VDD(I2C-bus) VDD(P) ADDR
C P0_3 P0_4
P0_1
P1_7 P1_6
D P0_5 P0_7
P1_2
P1_4 P1_5
E P0_6 VSS
P1_0
P1_1 P1_3
002aag244
Fig 5.
An empty cell indicates no ball
is populated at that grid point.
Ball mapping for 3 mm 3 mm
VFBGA24 (transparent top view)
PCAL6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 December 2012
© NXP B.V. 2012. All rights reserved.
5 of 54
datasheet
5 Page 
NXP Semiconductors
PCAL6416A
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
7.4 Register descriptions
7.4.1 Input port register pair (00h, 01h)
The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration
register. The Input port registers are read only; writes to these registers have no effect.
The default value ‘X’ is determined by the externally applied logic level. An Input port
register read operation is performed as described in Section 8.2.
Table 7. Input port 0 register (address 00h)
Bit 7 6 5 4 3 2 1 0
Symbol I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0
Default
X
X
X
X
X
X
X
X
Table 8. Input port 1 register (address 01h)
Bit 7 6 5 4 3 2 1 0
Symbol I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0
Default
X
X
X
X
X
X
X
X
7.4.2 Output port register pair (02h, 03h)
The Output port registers (registers 2 and 3) shows the outgoing logic levels of the pins
defined as outputs by the Configuration register. Bit values in these registers have no
effect on pins defined as inputs. In turn, reads from these registers reflect the value that
was written to these registers, not theh t t actualp : / / w w pinw . D value.a t a S h e Ae registert 4 U . n e t / pair write operation is
described in Section 8.1. A register pair read operation is described in Section 8.2.
Table 9.
Bit
Symbol
Default
Output port 0 register (address 02h)
7654
O0.7
O0.6
O0.5
O0.4
1111
3
O0.3
1
2
O0.2
1
1
O0.1
1
0
O0.0
1
Table 10.
Bit
Symbol
Default
Output port 1 register (address 03h)
7654
O1.7
O1.6
O1.5
O1.4
1111
3
O1.3
1
2
O1.2
1
1
O1.1
1
0
O1.0
1
PCAL6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 December 2012
© NXP B.V. 2012. All rights reserved.
11 of 54
datashe
11 Page | ||
| Páginas | Total 54 Páginas | |
| PDF Descargar | [ Datasheet PCAL6416A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PCAL6416A | Low-voltage translating 16-bit I2C-bus/SMBus I/O expander | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |