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PDF LGS-8913-B1 Data sheet ( Hoja de datos )

Número de pieza LGS-8913-B1
Descripción DMB-TH Demodulator ASIC
Fabricantes Legend Silicon 
Logotipo Legend Silicon Logotipo



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No Preview Available ! LGS-8913-B1 Hoja de datos, Descripción, Manual

DMB-TH Demodulator ASIC
LGS-8913-B1
“Kona-Digital”
http://www.DataSheet4U.net/
Product Specifications
October 2006
Revision 1.1
This document contains information that is proprietary and confidential to Legend Silicon Corp. and is intended for the specific
use of the recipient, for the purpose of evaluating or using Legend Silicon products. This document is provided to the recipient
with the expressed understanding that the recipient will not divulge its contents to other parties or otherwise misappropriate the
information contained herein.
US Patents Pending. DMB-TH and The Legend Silicon logo are registered trademarks of Legend Silicon Corp.
© 2006 Legend Silicon Corp. All rights reserved. All information is subject to change without notice.
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LGS-8913-B1 pdf
LGS-8913-B1
Product Specifications
2.3 Main DMB-TH Parameters for China DTV
PARAMETER
SPECIFICATION
DATA
Payload format
MPEG-2 transport stream
Payload rate formula
(188 bytes * 8 bits/byte * N) /
(frame length + guard interval)
FORWARD ERROR CORRECTION - OUTER
Format
BCH
FORWARD ERROR CORRECTION – INNER
LDPC
(7493,3048 / 4752 / 6096)
INTERLEAVING – INNER
Time interleaving (inter-frame):
Symbol-wise convolutional,
transport stream data only
branches = 52
Frequency interleaving (intra-frame):
Symbol-wise block
transport stream data and control data
TRANSMISSION PARAMETER SIGNALING (TPS)
TPS frequency
each OFDM frame
TPS length
72 bits
TPS modulation
4QAM
OFDM FRAME STRUCTURE
Symbols per frame
3780
Frame length
666.67, 571.43, or 500 µs
Sub-carrier spacing
1.5, 1.75, or 2.0 kHz
Guard interval duration
420 or 945 symbols
(1/9 or 1/4 of 3780)http://www.DataSheet4U.net/
Sub-carrier modulation
4QAM, 16QAM, or 64QAM
RF
Channel bandwidths
6 MHz, 7 MHz, or 8 MHz
Occupied bandwidths
5.95 MHz, 6.95 MHz, or 7.94 MHz
Pulse shaping filter
Square Root Raised Cosine
Transmission network
Single Frequency Network or
Multiple Frequency Network
NOTES
188 bytes per packet
N = 2, 3, or 4 for 4QAM, 4, 6 or 8 for
16QAM, 6, 9 or 12 for 64QAM
Tm 1: depth = 240 symbols
Tm 2: depth = 720 symbols
block size = 3780
36 symbols
3744 (FEC) + 36 (TPS)
For 6, 7, or 8 MHz
For 6, 7, or 8 MHz
Time = 1/9 or 1/4 of frame length
Uniform
alpha = 0.05
2.4 Framing Structure
DMB-TH signals are grouped in a series of hierarchical frames. The most basic element is the frame. In the frame there
are 3744 symbols that carry the data and 36 symbols that carry the Transmission Parameter Signaling (TPS). The TPS
carries information for the demodulator to automatically adapt to the incoming transmission such as: FEC inner code rate,
time interleaver length, etc.
In an 8 MHz channel, the 3780 sub-carriers are spaced at 2 kHz for a total occupied bandwidth of 7.56 MHz. In a 7 MHz
channel, the 3780 sub-carriers are spaced at 1.75 kHz for a total occupied bandwidth of 6.615 MHz. And in a 6 MHz
channel , the 3780 sub-carriers are spaced at 1.5 kHz for a total occupied bandwidth of 5.67 MHz.
A signal frame consists of a frame plus a guard interval. The guard interval length can either be the frame length divided
by 9 (420 symbols) or the frame length divided by 4 (945 symbols). See section 2.7 for more on the guard interval.
Legend Silicon Proprietary
Page 5
Revision 1.1 October 2006
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LGS-8913-B1 arduino
LGS-8913-B1
Product Specifications
3.2 Pin Table
All signal pins are 3.3V LVTTL compatible.
All input/output (IO) and output (O) pins can drive 4 mA, unless noted otherwise below.
I2C Interface (see Sections 4.1 & 4.2)
Pin #
70
71
66
67
24, 72, 73
Name
SCL
SDA
SCLT
SDAT
CE_A2, CE_A1, CE_A0
Type
I
IO
O
IO
I
Description
I2C clock
I2C data (open drain)
I2C clock pass-through for tuner
I2C data pass-through for tuner
I2C address selection (3 bits)
Clocks and Resets (see Section 4.3)
Pin #
33
34
28
Name
XTALIN
XTALOUT
RESET
Type
Analog
Analog
I
Description
external clock, use 60.8 XO
Reserved for 60.8XO
Hardware reset, active low
Front End & Tuner Interface (see Sections 4.4 through 4.7)
Pin #
62
49, 50, 51, 52, 53,
56, 57, 58, 59, 60
39, 40, 41, 42, 43,
44, 45, 46, 47, 48
61
Name
AGC
IF9 – IF0
Q9-Q0
IFCLK
Type
O
I
I
I
http://www.DataSheet4U.net/
Description
AGC output to tuner (PWM format)
IF input from ADC –or- I input from ADC in
Baseband mode
Drive to constant value in IF mode –or-
Q input from ADC in baseband mode
IF clk @ 30.4 Mhz
Time De-Interleaver Memory Interface (see Section 4.8)
(The pin ordering is optimized to facilitate trace routing to the SDRAM)
Pin #
84, 93, 83, 80, 79, 78,
77, 76, 87, 90, 91, 92
112, 111, 110, 107,
106, 116, 117, 118,
121, 122, 123, 126, 127
96, 97
100
101
86
85
102
Name
TI_A11 – TI_A0
TI_D12 – TI_D0
TI_BA1, TI_BA0
TI_CS
TI_RAS
TI_DQM
TI_CLK
TI_CAS
Type
O
IO
O
O
O
O
O
O
Description
Time de-interleaver memory address selection
(12 bits, A11 is MSB)
Time de-interleaver memory data
(13 bits, D12 is MSB)
Time de-interleaver memory bank select
Time de-interleaver memory chip select (active low)
Time de-interleaver memory row address strobe
(active low)
Time de-interleaver memory data mask
Time de-interleaver memory clock
Time de-interleaver memory column address strobe
(active low)
Legend Silicon Proprietary
Page 11
Revision 1.1 October 2006
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