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PDF K4S641632N Data sheet ( Hoja de datos )

Número de pieza K4S641632N
Descripción 64Mb N-die SDRAM
Fabricantes Samsung 
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K4S640832N
K4S641632N
Synchronous DRAM
64Mb N-die SDRAM Specification
54 TSOP-II
with Lead-Free and Halogen-Free
(RoHS compliant)
www.DataSheet.net/
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1 of 15
Rev. 1.11 March 2008
Datasheet pdf - http://www.DataSheet4U.co.kr/

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K4S641632N pdf
K4S640832N
K4S641632N
4.0 Package Physical Dimension
#54
#28
Synchronous DRAM
Unit : mm
#1
(1.50)
(R 0.15)
22.22 ± 0.10
(0.71)
0.80TYP
[0.80 ± 0.08]
Detail A
#27
(10°)
Detail B
(10°)
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS’Y OUT QUALITY
Detail A
Detail B
0.30
+0.10
- 0.05
0.35
+0.10
- 0.05
0.125
+0.075
- 0.035
0.10 MAX
[ 0.075 MAX
54Pin TSOP(II) Package Dimension
www.DataSheet.net/
0.25TYP
(0° ∼ 8°)
5 of 15
Rev. 1.11 March 2008
Datasheet pdf - http://www.DataSheet4U.co.kr/

5 Page





K4S641632N arduino
K4S640832N
K4S641632N
12.0 AC OPERATING TEST CONDITIONS
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Synchronous DRAM
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Unit
V
V
ns
V
Output
870
3.3V
1200
30pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Z0 = 50
Vtt = 1.4V
50
30pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
13.0 OPERATING AC PARAMETER
Parameter
Symbol
www.DataSheet.net/
50
(AC operating conditions unless otherwise noted)
Version
60
75
Unit
Note
Row active to row active delay
tRRD(min)
RAS to CAS delay
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to Active delay
tDAL(min)
Last data in to new col. address delay
tCDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
Number of valid output data
CAS latency = 3
CAS latency = 2
10 12 15
15 18 20
15 18 20
40 42 45
100
55 60 65
2
2 CLK + tRP
1
1
1
2
1
ns
ns
ns
ns
us
ns
CLK
-
CLK
CLK
CLK
ea
1
1
1
1
1, 6
2,5,6
5
2
2
3
4
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
6. tRC =tRFC, tRDL = tWR.
11 of 15
Rev. 1.11 March 2008
Datasheet pdf - http://www.DataSheet4U.co.kr/

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