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PDF PCA9624 Data sheet ( Hoja de datos )
| Número de pieza | PCA9624 | |
| Descripción | 8-bit Fm I2C-bus 100 mA 40 V LED driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCA9624
8-bit Fm+ I2C-bus 100 mA 40 V LED driver
Rev. 02 — 26 August 2009
Product data sheet
1. General description
The PCA9624 is an I2C-bus controlled 8-bit LED driver optimized for voltage switch
dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output
has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that
operates at 97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the
LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps)
group PWM controller has both a fixed frequency of 190 Hz and an adjustable frequency
between 24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 %
to 99.6 % that is used to either dim or blink all LEDs with the same value.
Each LED output can be off, on (no PWM control), set at its individual PWM controller
value or at both individual and group PWM controller values. The PCA9624 operates with
a supply voltage range of 2.3 V to 5.5 V and the 100 mA open-drain outputs allow
voltages up to 40 V.
The PCA9624 is one of the first LED controller devices in a new Fast-mode Plus (Fm+)
family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated bus
operation (up to 4000 pF).
The active LOW Output Enable input pin (OE) blinks all the LED outputs and can be used
to externally PWM the outputs, which is useful when multiple devices need to be dimmed
or blinked together without using softwarewww.DataSheet.net/ control.
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or
defined groups of PCA9624 devices to respond to a common I2C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time or marquee chasing
effect, thus minimizing I2C-bus commands. Seven hardware address pins allow up to
126 devices on the same bus.
The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9624
through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to
their default state causing the outputs to be set HIGH (LED off). This allows an easy and
quick way to reconfigure all device registers to the same condition.
The PCA9624 and PCA9634 software is identical and if the PCA9624 on-chip 100 mA
NAND FETs do not provide enough current or voltage to drive the LEDs, then the
PCA9634 with larger current or higher voltage external drivers can be used.
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
NXP Semiconductors
6. Pinning information
6.1 Pinning
PCA9624
8-bit Fm+ I2C-bus 100 mA 40 V LED driver
VSS 1
A0 2
A1 3
A2 4
A3 5
A4 6
VSS 7
LED0 8
LED1 9
LED2 10
LED3 11
VSS 12
PCA9624PW
24 VDD
23 SDA
22 SCL
21 A6
20 A5
19 OE
18 VSS
17 LED7
16 LED6
15 LED5
14 LED4
13 VSS
002aad593
Fig 2. Pin configuration for TSSOP
terminal 1
index area
A2
A3
A4
VSS
LED0
LED1
1
2
3
4
5
6
PCA9624BS
18 A6
17 A5
16 OE
15 VSS
14 LED7
13 LED6
Transparent top view
002aad594
Fig 3. Pin configuration for HVQFN24
6.2 Pin description
Table 2.
Symbol
VSS
A0
A1
A2
A3
A4
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
OE
A5
A6
SCL
SDA
VDD
Pin description
Pin
TSSOP24
1, 7, 12, 13, 18
2
3
4
5
6
8
9
10
11
14
15
16
17
19
20
21
22
23
24
www.DataSheet.net/
HVQFN24
4, 9, 22, 10, 15[1]
23
24
1
2
3
5
6
7
8
11
12
13
14
16
17
18
19
20
21
Type
power supply
I
I
I
I
I
O
O
O
O
O
O
O
O
I
I
I
I
I/O
power supply
PCA9624_2
Product data sheet
Rev. 02 — 26 August 2009
Description
supply ground
address input 0
address input 1
address input 2
address input 3
address input 4
LED driver 0
LED driver 1
LED driver 2
LED driver 3
LED driver 6
LED driver 7
LED driver 8
LED driver 9
active LOW output enable
address input 5
address input 6
serial clock line
serial data line
supply voltage
© NXP B.V. 2009. All rights reserved.
5 of 37
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
NXP Semiconductors
PCA9624
8-bit Fm+ I2C-bus 100 mA 40 V LED driver
7.3.3 PWM0 to PWM7, individual brightness control
Table 7. PWM0 to PWM7 - PWM registers 0 to 7 (address 02h to 09h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value
Description
02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle
03h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle
04h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle
05h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle
06h PWM4 7:0 IDC4[7:0] R/W 0000 0000* PWM4 Individual Duty Cycle
07h PWM5 7:0 IDC5[7:0] R/W 0000 0000* PWM5 Individual Duty Cycle
08h PWM6 7:0 IDC6[7:0] R/W 0000 0000* PWM6 Individual Duty Cycle
09h PWM7 7:0 IDC7[7:0] R/W 0000 0000* PWM7 Individual Duty Cycle
A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT3 registers).
duty cycle = -I--D-----C--2--x-5--[-6-7----:--0----]
(1)
7.3.4 GRPPWM, group duty cycle control
Table 8. GRPPWM - Group brightness control register (address 0Ah) bit description
Legend: * default value
www.DataSheet.net/
Address Register Bit Symbol Access Value
Description
0Ah GRPPWM 7:0 GDC[7:0] R/W 1111 1111 GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed
frequency signal is superimposed with the 97 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
duty cycle = G-----D-----2C---5-[--6-7---:--0----]
(2)
PCA9624_2
Product data sheet
Rev. 02 — 26 August 2009
© NXP B.V. 2009. All rights reserved.
11 of 37
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PCA9624.PDF ] | |
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